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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: dc5dcd13-fde0-4ca5-384b-08d686c4d2d7 X-MS-Exchange-CrossTenant-originalarrivaltime: 30 Jan 2019 15:08:41.3083 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR11MB1428 X-OriginatorOrg: microchip.com Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Tudor Ambarus Introduced in: commit b60557876849 ("ARM: dts: at91: sama5d2: switch to new clock binding"= ) Signed-off-by: Tudor Ambarus --- Documentation/devicetree/bindings/spi/atmel-quadspi.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/spi/atmel-quadspi.txt b/Docu= mentation/devicetree/bindings/spi/atmel-quadspi.txt index b93c1e2f25dd..e9dae6264d89 100644 --- a/Documentation/devicetree/bindings/spi/atmel-quadspi.txt +++ b/Documentation/devicetree/bindings/spi/atmel-quadspi.txt @@ -19,7 +19,7 @@ spi@f0020000 { reg =3D <0xf0020000 0x100>, <0xd0000000 0x8000000>; reg-names =3D "qspi_base", "qspi_mmap"; interrupts =3D <52 IRQ_TYPE_LEVEL_HIGH 7>; - clocks =3D <&spi0_clk>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 52>; #address-cells =3D <1>; #size-cells =3D <0>; pinctrl-names =3D "default"; --=20 2.9.5