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[209.132.180.67]) by mx.google.com with ESMTP id z63si3089397pfz.132.2019.01.30.18.34.48; Wed, 30 Jan 2019 18:35:03 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729767AbfAaCe1 (ORCPT + 99 others); Wed, 30 Jan 2019 21:34:27 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:5712 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725535AbfAaCe0 (ORCPT ); Wed, 30 Jan 2019 21:34:26 -0500 X-UUID: 244e67036a0c411e91eb3ee24e8c2c18-20190131 X-UUID: 244e67036a0c411e91eb3ee24e8c2c18-20190131 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 773714994; Thu, 31 Jan 2019 10:34:12 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 31 Jan 2019 10:34:10 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 31 Jan 2019 10:34:10 +0800 Message-ID: <1548902050.23230.4.camel@mtksdaap41> Subject: Re: [PATCH v6 6/6] arm64: dts: Add Mediatek SoC MT8183 and evaluation board dts and Makefile From: Erin Lo To: Rob Herring CC: Mark Rutland , Ben Ho , , Mengqi Zhang , , Hsin-Hsiung Wang , Weiyi Lu , "Seiya Wang" , , , , Jason Cooper , Marc Zyngier , , Matthias Brugger , Thomas Gleixner , , , srv_heupstream , Greg Kroah-Hartman , Stephen Boyd , , Zhiyong Tao Date: Thu, 31 Jan 2019 10:34:10 +0800 In-Reply-To: <20190130162204.GA1521@bogus> References: <1548317240-44682-1-git-send-email-erin.lo@mediatek.com> <1548317240-44682-7-git-send-email-erin.lo@mediatek.com> <20190130162204.GA1521@bogus> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-TM-SNTS-SMTP: 14330CE4A278BEFC08A742B7265A20949BB9CE8105936BB5CFA505010BB319132000:8 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 2019-01-30 at 10:22 -0600, Rob Herring wrote: > On Thu, Jan 24, 2019 at 04:07:20PM +0800, Erin Lo wrote: > > From: Ben Ho > > > > Add basic chip support for Mediatek 8183, include > > pinctrl file, uart node with correct uart clocks, pwrap device > > > > Add clock controller nodes, include topckgen, infracfg, > > apmixedsys and subsystem. > > > > Signed-off-by: Ben Ho > > Signed-off-by: Erin Lo > > Signed-off-by: Seiya Wang > > Signed-off-by: Zhiyong Tao > > Signed-off-by: Weiyi Lu > > Signed-off-by: Mengqi Zhang > > Signed-off-by: Hsin-Hsiung Wang > > Signed-off-by: Eddie Huang > > --- > > > > + sysirq: intpol-controller@c530a80 { > > interrupt-controller@... I will modify it in next version. > > > Place all the MMIO peripherals under one or more simple-bus nodes. > > Rob > Do you mean need to add simple-bus like this? + soc: soc { + #address-cells = <0x1>; + #size-cells = <0x1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; soc_data: soc_data@08000000 { compatible = "mediatek,mt8183-efuse", "mediatek,efuse"; reg = <0 0x08000000 0 0x0010>; #address-cells = <1>; #size-cells = <1>; status = "disabled"; }; gic: interrupt-controller@0c000000 { compatible = "arm,gic-v3"; #interrupt-cells = <4>; Best Regards, Erin > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek