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[209.132.180.67]) by mx.google.com with ESMTP id a124si4464076pfb.263.2019.01.31.04.02.08; Thu, 31 Jan 2019 04:02:24 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=FOsADNr6; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729892AbfAaMCB (ORCPT + 99 others); Thu, 31 Jan 2019 07:02:01 -0500 Received: from mail.kernel.org ([198.145.29.99]:36000 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726820AbfAaMCB (ORCPT ); Thu, 31 Jan 2019 07:02:01 -0500 Received: from bbrezillon (91-160-177-164.subs.proxad.net [91.160.177.164]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 201E5218D3; Thu, 31 Jan 2019 12:01:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1548936120; bh=v5FmM8JMbGh8lLfo05d49HXT0Cuq7wm2UMkiebkM2nY=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=FOsADNr6TrMlOSRO3YV0Heb0SOnP/CszRRKPRbnhhiVRUWq5kJIku8UMIW+cxbW1D VlNh2HWmTpyuNLAnFZAcfXdIRxavzOmIbRyGTxmn8cEL8cpG5Zc6TKHhKBnVVxIQo8 9au9Q6uYnHrmAxG0uKtHhhYdCAgqUMMXlxQ3jkGM= Date: Thu, 31 Jan 2019 13:01:50 +0100 From: Boris Brezillon To: Cc: , , , , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-spi@vger.kernel.org Subject: Re: [PATCH 9/9] spi: atmel-quadspi: add support for sam9x60 qspi controller Message-ID: <20190131130137.52b592f8@bbrezillon> In-Reply-To: <20190130150818.24902-10-tudor.ambarus@microchip.com> References: <20190130150818.24902-1-tudor.ambarus@microchip.com> <20190130150818.24902-10-tudor.ambarus@microchip.com> X-Mailer: Claws Mail 3.16.0 (GTK+ 2.24.32; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 30 Jan 2019 15:08:47 +0000 wrote: > +/* > + * atmel_qspi_set_address_mode() - set address mode. > + * @cfg: contains register values > + * @op: describes a SPI memory operation > + * > + * The controller allows 24 and 32-bit addressing while NAND-flash requires > + * 16-bit long. Handling 8-bit long addresses is done using the option field. > + * For the 16-bit addresses, the workaround depends of the number of requested > + * dummy bits. If there are 8 or more dummy cycles, the address is shifted and > + * sent with the first dummy byte. Otherwise opcode is disabled and the first > + * byte of the address contains the command opcode (works only if the opcode and > + * address use the same buswidth). The limitation is when the 16-bit address is > + * used without enough dummy cycles and the opcode is using a different buswidth > + * than the address. Too bad they didn't patch the IP to support 1 to 4 address bytes instead of only 3 or 4 :-(.