Received: by 2002:ad5:474a:0:0:0:0:0 with SMTP id i10csp7226913imu; Thu, 31 Jan 2019 07:02:29 -0800 (PST) X-Google-Smtp-Source: ALg8bN4YARJSvF4KUEmGDl01n701343Crt2Qrhy0gEtlC+PJMDZe4g0kFQfYPybfZMhxWeW6b+wR X-Received: by 2002:a63:d157:: with SMTP id c23mr31491731pgj.170.1548946949527; Thu, 31 Jan 2019 07:02:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1548946949; cv=none; d=google.com; s=arc-20160816; b=hsPcDnUdL3GsprtteDs3B+6OvlrA8E5LeqBjMyV2dumcMIPm9ZkcG3/DH0o+N283Eb lZnQiuuZnjEGdy6kno53RZzFqLR/EVqsJ8oPrmd3vRSon1Emyyr9T3nEH7ToNkLrc7hU K+T4A2zrE/kpIfeuoZo8qnzt1W7fvr3GIyMmAMXfA3iKlYF+6zolQ4yT0Oea8tvio+Hz pmtqTLM+2SsoUKhdDG/YJr7MsjUU8ha23uC/5JS1TmizDiCMyfQx5tO+aaXwa7T9Dliz FF3i2mmVg3FJW31pWFhNwZc4nY95uZ+Es3/GbkijiDB1WDF+7FZaDD0iNOJT8D2YQU2P 2bgw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=1X5MfRqa3ZlJcm7OWern5IDqYjUJQYr1pBu4z7fZ/Iw=; b=Z0RY3wNH4Sm81vcAWJE53x0HeppwQDAkKjHghub/sLZUqtKWO/4Lfd9mAvTLJW1Kbp FlNhvGoKQnfM6SJK0ywEH/C1Y91f9yxQM3Kzkcnf/viVQxu2gisaA3dhdccckkjUo3q8 n/2m5bpraqvgHLrMVSsPKXkX1anJl23Na/ah7GwawULjygLFyN7sOtoO95/iNBm3n+6K fN1FDpmdxjLq5/GrpVwkvRi+Y9L/SQLGlB6ypGRl6KKlYcV2xROTjtYPjLKC/QfE6fxp k2Z5a/bz0f3TgR74sxwJMVdI8WVCIxUOMQhzwslxtHO1FtI6uJovYkf7Tx3JtwGMVhfJ dvnQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a4si4903883pls.262.2019.01.31.07.02.11; Thu, 31 Jan 2019 07:02:29 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387677AbfAaPAU (ORCPT + 99 others); Thu, 31 Jan 2019 10:00:20 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:45792 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387621AbfAaPAP (ORCPT ); Thu, 31 Jan 2019 10:00:15 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 42C07169E; Thu, 31 Jan 2019 07:00:15 -0800 (PST) Received: from e112298-lin.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 49AE03F59C; Thu, 31 Jan 2019 07:00:13 -0800 (PST) From: Julien Thierry To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, daniel.thompson@linaro.org, joel@joelfernandes.org, marc.zyngier@arm.com, christoffer.dall@arm.com, james.morse@arm.com, catalin.marinas@arm.com, will.deacon@arm.com, mark.rutland@arm.com, Julien Thierry Subject: [PATCH v10 25/25] arm64: Enable the support of pseudo-NMIs Date: Thu, 31 Jan 2019 14:59:03 +0000 Message-Id: <1548946743-38979-26-git-send-email-julien.thierry@arm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1548946743-38979-1-git-send-email-julien.thierry@arm.com> References: <1548946743-38979-1-git-send-email-julien.thierry@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add a build option and a command line parameter to build and enable the support of pseudo-NMIs. Signed-off-by: Julien Thierry Suggested-by: Daniel Thompson Cc: Catalin Marinas Cc: Will Deacon --- Documentation/admin-guide/kernel-parameters.txt | 5 +++++ arch/arm64/Kconfig | 14 ++++++++++++++ arch/arm64/kernel/cpufeature.c | 10 +++++++++- 3 files changed, 28 insertions(+), 1 deletion(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index b799bcf..4d85fa5 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -1831,6 +1831,11 @@ to let secondary kernels in charge of setting up LPIs. + irqchip.gicv3_pseudo_nmi= [ARM64] + Enables support for pseudo-NMIs in the kernel. This + requires the kernel to be built with + CONFIG_ARM64_PSEUDO_NMI. + irqfixup [HW] When an interrupt is not handled search all handlers for it. Intended to get systems with badly broken diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index a4168d3..702198f 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -1328,6 +1328,20 @@ config ARM64_MODULE_PLTS bool select HAVE_MOD_ARCH_SPECIFIC +config ARM64_PSEUDO_NMI + bool "Support for NMI-like interrupts" + select CONFIG_ARM_GIC_V3 + help + Adds support for mimicking Non-Maskable Interrupts through the use of + GIC interrupt priority. This support requires version 3 or later of + Arm GIC. + + This high priority configuration for interrupts needs to be + explicitly enabled by setting the kernel parameter + "irqchip.gicv3_pseudo_nmi" to 1. + + If unsure, say N + config RELOCATABLE bool help diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index b530fb24..e24e94d 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -1207,10 +1207,18 @@ static void cpu_enable_address_auth(struct arm64_cpu_capabilities const *cap) #endif /* CONFIG_ARM64_PTR_AUTH */ #ifdef CONFIG_ARM64_PSEUDO_NMI +static bool enable_pseudo_nmi; + +static int __init early_enable_pseudo_nmi(char *p) +{ + return strtobool(p, &enable_pseudo_nmi); +} +early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); + static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, int scope) { - return false; + return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope); } #endif -- 1.9.1