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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 0c971f3e-7c53-43af-9658-08d6879750e9 X-MS-Exchange-CrossTenant-originalarrivaltime: 31 Jan 2019 16:15:25.7446 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR11MB1874 X-OriginatorOrg: microchip.com Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Tudor Ambarus Cache MR value to avoid write access when setting the controller in Serial Memory Mode (SMM). SMM is set in exec_op() and not at probe time, to let room for future regular SPI support. Signed-off-by: Tudor Ambarus --- v2: cache MR value instead of moving the write access at probe drivers/spi/atmel-quadspi.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c index ddc712410812..fe05aee5d845 100644 --- a/drivers/spi/atmel-quadspi.c +++ b/drivers/spi/atmel-quadspi.c @@ -155,6 +155,7 @@ struct atmel_qspi { struct clk *clk; struct platform_device *pdev; u32 pending; + u32 mr; struct completion cmd_completion; }; =20 @@ -238,7 +239,9 @@ static int atmel_qspi_exec_op(struct spi_mem *mem, cons= t struct spi_mem_op *op) icr =3D QSPI_ICR_INST(op->cmd.opcode); ifr =3D QSPI_IFR_INSTEN; =20 - qspi_writel(aq, QSPI_MR, QSPI_MR_SMM); + /* Set the QSPI controller in Serial Memory Mode */ + if (!(aq->mr & QSPI_MR_SMM)) + qspi_writel(aq, QSPI_MR, QSPI_MR_SMM); =20 mode =3D find_mode(op); if (mode < 0) --=20 2.9.5