Received: by 2002:ac0:8c9a:0:0:0:0:0 with SMTP id r26csp398178ima; Thu, 31 Jan 2019 19:14:56 -0800 (PST) X-Google-Smtp-Source: AHgI3Ia2OKgdga/W1rXetgqSCoPvTkfqT9t4rW/fCb8yT6Y5MZ+7UD0gudXm9SZkWI+thYebRtA3 X-Received: by 2002:a63:fc49:: with SMTP id r9mr578722pgk.209.1548990896872; Thu, 31 Jan 2019 19:14:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1548990896; cv=none; d=google.com; s=arc-20160816; b=jkEPO97b5fBGOO2SBhm6GaYb3zql3bRyjg6Rtojs5O8IX1EOnE0p6pOdgU8FATzF5l +U025CArv83ia7PRvxSpheRCbCC+Qj/stcL7lLahlK+vsuS3b66k1s5yMc1DPiqLkPVj xONh0IClJIop8Sto6d/iEUM4QMH8+HHuaGKHtsnueGpwCWMHUMFwHQDJAC22yILe6e4W j8JgSU3M0Q6PNMaLo1Q81ZftIzIsRyi9YmOwxydqILHwS+SV6/i+LY/ASf59353gNi3l Rn1VnwSafK0KAmKAMEZI70qw6BmKi3p4uxZBcsSFlhkNmOcxZ4XLQCV8GXP2GQScdVO/ YH6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:content-transfer-encoding :references:in-reply-to:date:cc:to:from:subject:message-id; bh=3ZNLR075Y+ReKqAgR8daRrRAQJDyPeAxblM74SD1Od8=; b=h4uylC7uhuZR7D4EtjqsFUMP+8NgP1Tbqkd7mLLjAeQL97l3gyx4QEALHAgSftCFfD X9824deIxlZqF3fUqbLXMVHSoLT8OqsDanPG8LzDLZkPIrMEbcGUR47aZQ5llyB89zf9 JSlkLcjH9UuXaIZLMC6bj1lDn9DD0n2xWVWzTzeJ2CJNjY/tftTAm3MUutBAxmcrYl36 Qz4BcSi7Q7x7ybDUVGahzOLzG5R51D7xL8teJJ0srmNiKo72SuPeqgAb/j7jd86QEj67 IzoB9nG8ecy1jBhV5ob6iArTMfu5bha9+SLIypGPiMFsadEupfROAiEXqBKNzqc+QkH5 snkg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d2si6278544pla.81.2019.01.31.19.14.41; Thu, 31 Jan 2019 19:14:56 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726973AbfBABi2 (ORCPT + 99 others); Thu, 31 Jan 2019 20:38:28 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:30554 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726425AbfBABi2 (ORCPT ); Thu, 31 Jan 2019 20:38:28 -0500 X-UUID: 7bf840b21c78462d82058e3f38702b8b-20190201 X-UUID: 7bf840b21c78462d82058e3f38702b8b-20190201 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1066291908; Fri, 01 Feb 2019 09:38:17 +0800 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by mtkmbs03n2.mediatek.inc (172.21.101.182) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 1 Feb 2019 09:38:13 +0800 Received: from [10.17.3.153] (10.17.3.153) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Fri, 1 Feb 2019 09:38:12 +0800 Message-ID: <1548985091.10251.26.camel@mhfsdcap03> Subject: Re: [PATCH] mmc: mmc: Fix HS setting in mmc_hs400_to_hs200() From: Chaotian Jing To: Ulf Hansson CC: Matthias Brugger , Shawn Lin , Simon Horman , "Kyle Roeschley" , Hongjie Fang , Harish Jenny K N , "linux-mmc@vger.kernel.org" , Linux Kernel Mailing List , Linux ARM , , srv_heupstream Date: Fri, 1 Feb 2019 09:38:11 +0800 In-Reply-To: References: <1548921212-5219-1-git-send-email-chaotian.jing@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.2.3-0ubuntu6 Content-Transfer-Encoding: 7bit MIME-Version: 1.0 X-TM-SNTS-SMTP: B537CDA27EF59E3B1B84E492B269AE1FB2207C44900CE4F37535641C42AF7ECF2000:8 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 2019-01-31 at 16:58 +0100, Ulf Hansson wrote: > On Thu, 31 Jan 2019 at 08:53, Chaotian Jing wrote: > > > > mmc_hs400_to_hs200() begins with the card and host in HS400 mode. > > Therefore, any commands sent to the card should use HS400 timing. > > It is incorrect to reduce frequency to 50Mhz before sending the switch > > command, in this case, only reduce clock frequency to 50Mhz but without > > host timming change, host is still in hs400 mode but clock changed from > > 200Mhz to 50Mhz, which makes the tuning result unsuitable and cause > > the switch command gets response CRC error. > > According the eMMC spec there is no violation by decreasing the clock > frequency like this. We can use whatever value <=200MHz. > > However, perhaps in practice this becomes an issue, due to the tuning > for HS400 has been done on the "current" frequency. > > As as start, I think you need to clarify this in the changelog. > Yes, reduce clock frequency to 50Mhz is no Spec violation, but it may cause __mmc_switch() gets response CRC error, decreasing the clock but without HOST mode change, on the host side, host driver do not know what's operation the core layer want to do and can only set current bus clock to 50Mhz, without tuning parameter change, it has a chance lead to response CRC error. even lower clock frequency, but with the wrong tuning parameter setting(the setting is of hs400 tuning @200Mhz). > > > > this patch refers to mmc_select_hs400(), make the reduce clock frequency > > after card timing change. > > > > Signed-off-by: Chaotian Jing > > --- > > drivers/mmc/core/mmc.c | 8 ++++---- > > 1 file changed, 4 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c > > index da892a5..21b811e 100644 > > --- a/drivers/mmc/core/mmc.c > > +++ b/drivers/mmc/core/mmc.c > > @@ -1239,10 +1239,6 @@ int mmc_hs400_to_hs200(struct mmc_card *card) > > int err; > > u8 val; > > > > - /* Reduce frequency to HS */ > > - max_dtr = card->ext_csd.hs_max_dtr; > > - mmc_set_clock(host, max_dtr); > > - > > As far as I can tell, the reason to why we change the clock frequency > *before* the call to __mmc_switch() below, is probably to try to be on > the safe side and conform to the spec. > Agree, it Must be more safe with lower clock frequency, but the precondition is to make the host side recognize current timing is not HS400 mode. it has no method to find a safe setting to ensure no response CRC error when reduce clock from 200Mhz to 50Mhz. > However, I think you have a point, as the call to __mmc_switch(), > passes the "send_status" parameter as false, no other command than the > CMD6 is sent to the card. > yes, the send status command was sent only after __mmc_switch() done. > > /* Switch HS400 to HS DDR */ > > val = EXT_CSD_TIMING_HS; > > err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, > > @@ -1253,6 +1249,10 @@ int mmc_hs400_to_hs200(struct mmc_card *card) > > > > mmc_set_timing(host, MMC_TIMING_MMC_DDR52); > > > > + /* Reduce frequency to HS */ > > + max_dtr = card->ext_csd.hs_max_dtr; > > + mmc_set_clock(host, max_dtr); > > + > > Perhaps it's even more correct to change the clock frequency before > the call to mmc_set_timing(host, MMC_TIMING_MMC_DDR52). Otherwise you > will be using the DDR52 timing in the controller, but with a too high > frequency. > for Our host, it has no impact to change the clock before or after change timing, as the mmc_set_timing() is only for host side, not related to MMC card side and no commands sent do card before the timing/clock change completed. > > err = mmc_switch_status(card); > > if (err) > > goto out_err; > > -- > > 1.8.1.1.dirty > > > > Finally, it sounds like you are trying to fix a real problem, can you > please provide some more information what is happening when the > problem occurs at your side? > Yes, I got a problem with new kernel version. with commit:57da0c042f4af52614f4bd1a148155a299ae5cd8, this commit makes re-tuning every time when access RPMB partition. in fact, our host tuning result of hs400 is very stable and almost never get response CRC error with clock frequency at 200Mhz. but cannot ensure this tuning result also suitable when running at HS400 mode @50Mhz. as I mentioned before, the host side does not know the reason of reduce clock frequency to 50Mhz at HS400 mode, so what's the host side can do is only reduce the bus clock to 50Mhz, even it can just only set the tuning setting to default when clock frequency lower than 50Mhz, but both card & host side are still at HS400 mode, still cannot ensure this setting is suitable. > Kind regards > Uffe