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[209.132.180.67]) by mx.google.com with ESMTP id s13si6738729pgc.509.2019.02.01.00.00.50; Fri, 01 Feb 2019 00:01:06 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=afmZo3YG; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728316AbfBAH5v (ORCPT + 99 others); Fri, 1 Feb 2019 02:57:51 -0500 Received: from mail.kernel.org ([198.145.29.99]:40046 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726526AbfBAH5v (ORCPT ); Fri, 1 Feb 2019 02:57:51 -0500 Received: from bbrezillon (91-160-177-164.subs.proxad.net [91.160.177.164]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 089472084A; Fri, 1 Feb 2019 07:57:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1549007870; bh=mPW1kdJvdfWF8y1sFgd0mQFVOp3ErO00h4ymz2Z7ngI=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=afmZo3YG5x42LIXPyg6Bm3iewdgEtE7goI9bXwIQwsV3K6N1ZexItakuNwT+Jz0a8 QyACpsKz63wNVbrmy1SOxunh0feg3PF/B7DR6g1dvk55dZJ3N++8KTdXjvWUyMuWR1 M5vWP2UyMPd6JboVkhANvPPQByydSBi8aN1Hiff8= Date: Fri, 1 Feb 2019 08:57:39 +0100 From: Boris Brezillon To: Cc: , , , , , , , , , , Subject: Re: [PATCH v2 10/10] spi: atmel-quadspi: add support for sam9x60 qspi controller Message-ID: <20190201085739.775add3f@bbrezillon> In-Reply-To: <947f148d-3fd8-4e7d-4301-9d67715fbf7d@microchip.com> References: <20190131161515.21605-1-tudor.ambarus@microchip.com> <20190131161515.21605-11-tudor.ambarus@microchip.com> <20190131173207.56481a42@bbrezillon> <947f148d-3fd8-4e7d-4301-9d67715fbf7d@microchip.com> X-Mailer: Claws Mail 3.16.0 (GTK+ 2.24.32; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 1 Feb 2019 07:07:40 +0000 wrote: > > > >> #define QSPI_IFR_TFRTYP_MASK GENMASK(13, 12) > >> #define QSPI_IFR_TFRTYP_TRSFR_READ (0 << 12) > >> #define QSPI_IFR_TFRTYP_TRSFR_READ_MEM (1 << 12) > > > > Looks like the read/write flag is on bit 13. Can we just add > > for sama5d2 only Feel free to prefix macros with the SoC name to make it clear: #define QSPI_IFR_SAMA5D2_WRITE_TRSFR BIT(13) > > > > > #define QSPI_IFR_TFRTYP_TRSFR_WRITE BIT(13) > > > > and drop all others def? This way the implementation is consistent > > between sam9x60 and sama5d2. > > BIT(13) has no meaning for sam9x60. I can drop the macros with zero value for > sama5d2 in a separate patch. > > > >> +#define QSPI_IFR_APBTFRTYP_READ BIT(24) And this one would be define QSPI_IFR_SAM9X60_READ_TRSFR BIT(24) > >> > >> /* Bitfields in QSPI_SMR (Scrambling Mode Register) */ > >> #define QSPI_SMR_SCREN BIT(0) > >> @@ -137,16 +144,37 @@ > >> #define QSPI_WPSR_WPVSRC(src) (((src) << 8) & QSPI_WPSR_WPVSRC) > >> > >> > >> +/* Describes register values. */ > >> +struct atmel_qspi_cfg { > >> + u32 icr; > >> + u32 iar; > >> + u32 ifr; > >> +}; > >> + > >> +struct atmel_qspi_caps; > >> + > >> struct atmel_qspi { > >> void __iomem *regs; > >> void __iomem *mem; > >> struct clk *clk; > > > > Can we rename that on pclk? > > will rename it, together with the support for unnamed clock of sama5d2 in a separate > patch. The dt-bindings patch that imposes "pclk" for sama5d2 should be separated too. Sounds good.