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[209.132.180.67]) by mx.google.com with ESMTP id x5si7179241pgq.535.2019.02.01.05.10.35; Fri, 01 Feb 2019 05:10:51 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b=G+hixDN+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730208AbfBAMoX (ORCPT + 99 others); Fri, 1 Feb 2019 07:44:23 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:10034 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726450AbfBAMoR (ORCPT ); Fri, 1 Feb 2019 07:44:17 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 01 Feb 2019 04:43:33 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Fri, 01 Feb 2019 04:44:15 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Fri, 01 Feb 2019 04:44:15 -0800 Received: from [10.26.11.142] (10.124.1.5) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 1 Feb 2019 12:44:12 +0000 Subject: Re: [PATCH V5 2/7] clocksource: tegra: add Tegra210 timer support To: Joseph Lo , Thierry Reding , Daniel Lezcano , Thomas Gleixner CC: , , , Thierry Reding References: <20190201033621.16814-1-josephl@nvidia.com> <20190201033621.16814-3-josephl@nvidia.com> From: Jon Hunter Message-ID: <5490ad66-7d20-7093-7025-1d0ec8da6dec@nvidia.com> Date: Fri, 1 Feb 2019 12:44:10 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: <20190201033621.16814-3-josephl@nvidia.com> X-Originating-IP: [10.124.1.5] X-ClientProxiedBy: HQMAIL105.nvidia.com (172.20.187.12) To HQMAIL101.nvidia.com (172.20.187.10) Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1549025013; bh=ExmvwM7XhJSLttWMoVXIQfFt7vVOAaLH3dfMWK45owM=; h=X-PGP-Universal:Subject:To:CC:References:From:Message-ID:Date: User-Agent:MIME-Version:In-Reply-To:X-Originating-IP: X-ClientProxiedBy:Content-Type:Content-Language: Content-Transfer-Encoding; b=G+hixDN+1CRcYtsH7X9zWudXlYPzGqYb4CBUk0yldDKTUcqdgfxIjHT1bVz2sw0YQ JqLTz5wtyqj2pszPS9ApEjsuRhhqu35J8e+BJpt/DD8TvfNkHhOgnx4gNfNW6o2gaa 7oYZQdhS4TRjlUfFE+fflsgfjQwPy3vKOWt4ygxmgquF6sWvbyyExxAmw2g4t5g864 1XdHV7iAUf8YLNzTQ3zgs5k9U5+x61T7jpZqQgiyry0UTSp3gBvABKAqinD67G1YIG qLjt/yXGP8oDJzEC4fzhCPzY1Wla7KG62i2kiZoroWA/tqbVMTpZlubxwQC1rnmyLB irwce0qwlm0jA== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 01/02/2019 03:36, Joseph Lo wrote: > Add support for the Tegra210 timer that runs at oscillator clock > (TMR10-TMR13). We need these timers to work as clock event device and to > replace the ARMv8 architected timer due to it can't survive across the > power cycle of the CPU core or CPUPORESET signal. So it can't be a wake-up > source when CPU suspends in power down state. > > Also convert the original driver to use timer-of API. It may have been nice to split this into 2 patches to make it easier to see what is going on but not a big deal. > Cc: Daniel Lezcano > Cc: Thomas Gleixner > Cc: linux-kernel@vger.kernel.org > Signed-off-by: Joseph Lo > Acked-by: Thierry Reding > --- > v5: > * add ack tag from Thierry > v4: > * merge timer-tegra210.c in previous version into timer-tegra20.c > v3: > * use timer-of API > v2: > * add error clean-up code > --- > drivers/clocksource/Kconfig | 2 +- > drivers/clocksource/timer-tegra20.c | 369 ++++++++++++++++++++-------- > include/linux/cpuhotplug.h | 1 + > 3 files changed, 272 insertions(+), 100 deletions(-) > > diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig > index a9e26f6a81a1..6af78534a285 100644 > --- a/drivers/clocksource/Kconfig > +++ b/drivers/clocksource/Kconfig > @@ -131,7 +131,7 @@ config SUN5I_HSTIMER > config TEGRA_TIMER > bool "Tegra timer driver" if COMPILE_TEST > select CLKSRC_MMIO > - depends on ARM > + select TIMER_OF > help > Enables support for the Tegra driver. > > diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c > index 4293943f4e2b..96a809341c9b 100644 > --- a/drivers/clocksource/timer-tegra20.c > +++ b/drivers/clocksource/timer-tegra20.c > @@ -15,21 +15,24 @@ > * > */ > > -#include > +#include > +#include > +#include > +#include > +#include > #include > -#include > #include > -#include > -#include > -#include > -#include > -#include > #include > #include > -#include > -#include > +#include > +#include > +#include > + > +#include "timer-of.h" > > +#ifdef CONFIG_ARM > #include > +#endif > > #define RTC_SECONDS 0x08 > #define RTC_SHADOW_SECONDS 0x0c > @@ -43,70 +46,147 @@ > #define TIMER2_BASE 0x8 > #define TIMER3_BASE 0x50 > #define TIMER4_BASE 0x58 > - > -#define TIMER_PTV 0x0 > -#define TIMER_PCR 0x4 > - > +#define TIMER10_BASE 0x90 > + > +#define TIMER_PTV 0x0 > +#define TIMER_PTV_EN BIT(31) > +#define TIMER_PTV_PER BIT(30) > +#define TIMER_PCR 0x4 > +#define TIMER_PCR_INTR_CLR BIT(30) > + > +#ifdef CONFIG_ARM > +#define TIMER_BASE TIMER3_BASE > +#else > +#define TIMER_BASE TIMER10_BASE > +#endif > +#define TIMER10_IRQ_IDX 10 > +#define TIMER_FOR_CPU(cpu) (TIMER_BASE + (cpu) * 8) > +#define IRQ_IDX_FOR_CPU(cpu) (TIMER10_IRQ_IDX + cpu) TIMER10_IRQ_IDX and IRQ_IDX_FOR_CPU are only applicable to ARM64 and so we should probably not defined for ARM to avoid any confusion. Furthermore, a lot of these TIMERx_BASE definitions are unused AFAICT. Would be good to get rid of these. Maybe we could just have ... +#ifdef CONFIG_ARM +#define TIMER_CPU0 3 +#else +#define TIMER_CPU0 10 +#endif +#define TIMER_BASE_FOR_CPU(cpu) ((TIMER_CPU0 + cpu) * 8) +#define TIMER_FOR_CPU(cpu) (TIMER_CPU0 + cpu) Otherwise looks good to me. Cheers Jon -- nvpublic