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[209.132.180.67]) by mx.google.com with ESMTP id o68si9065132pfo.140.2019.02.01.08.33.25; Fri, 01 Feb 2019 08:33:42 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b=nh91QHfT; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730205AbfBAQbk (ORCPT + 99 others); Fri, 1 Feb 2019 11:31:40 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:9798 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726486AbfBAQbk (ORCPT ); Fri, 1 Feb 2019 11:31:40 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 01 Feb 2019 08:31:09 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Fri, 01 Feb 2019 08:31:38 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 01 Feb 2019 08:31:38 -0800 Received: from [10.26.11.142] (10.124.1.5) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 1 Feb 2019 16:31:35 +0000 Subject: Re: [PATCH V6 2/7] clocksource: tegra: add Tegra210 timer support To: Joseph Lo , Thierry Reding , Daniel Lezcano , Thomas Gleixner CC: , , , Thierry Reding References: <20190201161654.18315-1-josephl@nvidia.com> <20190201161654.18315-3-josephl@nvidia.com> From: Jon Hunter Message-ID: <0272983e-bbff-601e-67fa-2cb9e852a68c@nvidia.com> Date: Fri, 1 Feb 2019 16:31:32 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: <20190201161654.18315-3-josephl@nvidia.com> X-Originating-IP: [10.124.1.5] X-ClientProxiedBy: HQMAIL104.nvidia.com (172.18.146.11) To HQMAIL101.nvidia.com (172.20.187.10) Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1549038669; bh=Z3TBZLUsIQJVIrzd6oArMDFQiN6OmVKCFtkPHZXblVQ=; h=X-PGP-Universal:Subject:To:CC:References:From:Message-ID:Date: User-Agent:MIME-Version:In-Reply-To:X-Originating-IP: X-ClientProxiedBy:Content-Type:Content-Language: Content-Transfer-Encoding; b=nh91QHfT/JL0gSkjMgFgDnxjZWeOdzBhKay+bXhrwYzZx0fouti5KJ9Tq7fo+wqDp cLMA3LXvTurBCd8vAK8Z9GpfKWh+NNw3/p6y79IkCXDMk0usKMnTcZGtUhBboQPBY/ iIXCFj5qaHkFIc/2fVnZwER4jeiCeAoc1qvnSfoMcUAkur1EJId+QwjWdr4+rMSVsz cbUzESKU2bfjRrUfga04dECuOoMOGsDKldmM8GVIKvrdgRwqOxOJMrHMqo//dCVArc mdg+DeRs1zjxOUf4xve+7YqO1+A+L02gkQAyP8QJtr5Bp8Pyp2Il62MrpDxsTSV1l4 vIbyPo4YHvVzA== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 01/02/2019 16:16, Joseph Lo wrote: > Add support for the Tegra210 timer that runs at oscillator clock > (TMR10-TMR13). We need these timers to work as clock event device and to > replace the ARMv8 architected timer due to it can't survive across the > power cycle of the CPU core or CPUPORESET signal. So it can't be a wake-up > source when CPU suspends in power down state. > > Also convert the original driver to use timer-of API. > > Cc: Daniel Lezcano > Cc: Thomas Gleixner > Cc: linux-kernel@vger.kernel.org > Signed-off-by: Joseph Lo > Acked-by: Thierry Reding > Acked-by: Jon Hunter > --- > v6: > * refine the timer defines > * add ack tag from Jon. > v5: > * add ack tag from Thierry > v4: > * merge timer-tegra210.c in previous version into timer-tegra20.c > v3: > * use timer-of API > v2: > * add error clean-up code > --- > drivers/clocksource/Kconfig | 2 +- > drivers/clocksource/timer-tegra20.c | 371 ++++++++++++++++++++-------- > include/linux/cpuhotplug.h | 1 + > 3 files changed, 270 insertions(+), 104 deletions(-) > > diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig > index a9e26f6a81a1..6af78534a285 100644 > --- a/drivers/clocksource/Kconfig > +++ b/drivers/clocksource/Kconfig > @@ -131,7 +131,7 @@ config SUN5I_HSTIMER > config TEGRA_TIMER > bool "Tegra timer driver" if COMPILE_TEST > select CLKSRC_MMIO > - depends on ARM > + select TIMER_OF > help > Enables support for the Tegra driver. > > diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c > index 4293943f4e2b..f66edd63d7f4 100644 > --- a/drivers/clocksource/timer-tegra20.c > +++ b/drivers/clocksource/timer-tegra20.c > @@ -15,21 +15,24 @@ > * > */ > > -#include > +#include > +#include > +#include > +#include > +#include > #include > -#include > #include > -#include > -#include > -#include > -#include > -#include > #include > #include > -#include > -#include > +#include > +#include > +#include > + > +#include "timer-of.h" > > +#ifdef CONFIG_ARM > #include > +#endif > > #define RTC_SECONDS 0x08 > #define RTC_SHADOW_SECONDS 0x0c > @@ -39,74 +42,145 @@ > #define TIMERUS_USEC_CFG 0x14 > #define TIMERUS_CNTR_FREEZE 0x4c > > -#define TIMER1_BASE 0x0 > -#define TIMER2_BASE 0x8 > -#define TIMER3_BASE 0x50 > -#define TIMER4_BASE 0x58 > - > -#define TIMER_PTV 0x0 > -#define TIMER_PCR 0x4 > - > +#define TIMER_PTV 0x0 > +#define TIMER_PTV_EN BIT(31) > +#define TIMER_PTV_PER BIT(30) > +#define TIMER_PCR 0x4 > +#define TIMER_PCR_INTR_CLR BIT(30) > + > +#ifdef CONFIG_ARM > +#define TIMER_CPU0 0x50 /* TIMER3 */ > +#else > +#define TIMER_CPU0 0x90 /* TIMER10 */ > +#define TIMER10_IRQ_IDX 10 > +#define IRQ_IDX_FOR_CPU(cpu) (TIMER10_IRQ_IDX + cpu) > +#endif > +#define TIMER_BASE_FOR_CPU(cpu) (TIMER_CPU0 + (cpu) * 8) So maybe I was not being clear, but what I meant was you replace 'IRQ_IDX_FOR_CPU(cpu)' with 'TIMER_FOR_CPU(cpu), because technically, we just need to know the timer index being used for a given CPU to lookup the associated interrupt. And so I was suggesting you make a generic macro that could be used for both 32-bit and 64-bit ARM. However, given that currently we do not need/use this for 32-bit ARM it is really a mute point. However, don't bother changing this now and you have included my ACK, so we are all good. Thanks! Jon -- nvpublic