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Reply-To: cwchoi00@gmail.com
From:   Chanwoo Choi <cwchoi00@gmail.com>
Date:   Sun, 3 Feb 2019 16:54:09 +0900
Message-ID: <CAGTfZH05zn_FiNt3zSHZJfspvo4RXWPrAtWLUq5xsqKoB3qxBA@mail.gmail.com>
Subject: Re: [PATCH v3 3/8] clk: samsung: add BPLL rate table for Exynos 5422 SoC
To:     Lukasz Luba <l.luba@partner.samsung.com>
Cc:     Chanwoo Choi <cw00.choi@samsung.com>,
        devicetree <devicetree@vger.kernel.org>,
        linux-kernel <linux-kernel@vger.kernel.org>,
        Linux PM list <linux-pm@vger.kernel.org>,
        linux-samsung-soc <linux-samsung-soc@vger.kernel.org>,
        Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>,
        Krzysztof Kozlowski <krzk@kernel.org>,
        Kukjin Kim <kgene@kernel.org>,
        Kyungmin Park <kyungmin.park@samsung.com>,
        Marek Szyprowski <m.szyprowski@samsung.com>,
        Sylwester Nawrocki <s.nawrocki@samsung.com>,
        MyungJoo Ham <myungjoo.ham@samsung.com>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>, linux-clk@vger.kernel.org,
        linux-arm-kernel <linux-arm-kernel@lists.infradead.org>
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Sender: linux-kernel-owner@vger.kernel.org
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Hi Lukasz,

2019=EB=85=84 2=EC=9B=94 1=EC=9D=BC (=EA=B8=88) =EC=98=A4=ED=9B=84 11:22, L=
ukasz Luba <l.luba@partner.samsung.com>=EB=8B=98=EC=9D=B4 =EC=9E=91=EC=84=
=B1:

>
> Hi Chanwoo,
>
> On 2/1/19 9:44 AM, Chanwoo Choi wrote:
> > Hi,
> >
> > On 19. 1. 31. =EC=98=A4=ED=9B=84 5:49, Lukasz Luba wrote:
> >> Add new table rate for BPLL for Exynos5422 SoC supporting Dynamic Memo=
ry
> >> Controller frequencies for driver's DRAM timings.
> >>
> >> CC: Sylwester Nawrocki <s.nawrocki@samsung.com>
> >> CC: Chanwoo Choi <cw00.choi@samsung.com>
> >> CC: Michael Turquette <mturquette@baylibre.com>
> >> CC: Stephen Boyd <sboyd@kernel.org>
> >> CC: Kukjin Kim <kgene@kernel.org>
> >> CC: Krzysztof Kozlowski <krzk@kernel.org>
> >> CC: linux-samsung-soc@vger.kernel.org
> >> CC: linux-clk@vger.kernel.org
> >> CC: linux-arm-kernel@lists.infradead.org
> >> CC: linux-kernel@vger.kernel.org
> >> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
> >> ---
> >>   drivers/clk/samsung/clk-exynos5420.c | 15 ++++++++++++++-
> >>   1 file changed, 14 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsun=
g/clk-exynos5420.c
> >> index 3e87421..8bf9579 100644
> >> --- a/drivers/clk/samsung/clk-exynos5420.c
> >> +++ b/drivers/clk/samsung/clk-exynos5420.c
> >> @@ -1325,6 +1325,19 @@ static const struct samsung_pll_rate_table exyn=
os5420_pll2550x_24mhz_tbl[] __ini
> >>      PLL_35XX_RATE(24 * MHZ, 200000000,  200, 3, 3),
> >>   };
> >>
> >> +static const struct samsung_pll_rate_table exynos5422_bpll_rate_table=
[] =3D {
> >> +    PLL_35XX_RATE(24 * MHZ, 933000000, 311, 4, 1),
> >> +    PLL_35XX_RATE(24 * MHZ, 825000000, 275, 4, 1),
> >> +    PLL_35XX_RATE(24 * MHZ, 728000000, 182, 3, 1),
> >> +    PLL_35XX_RATE(24 * MHZ, 633000000, 211, 4, 1),
> >> +    PLL_35XX_RATE(24 * MHZ, 543000000, 181, 2, 2),
> >> +    PLL_35XX_RATE(24 * MHZ, 413000000, 413, 6, 2),
> >> +    PLL_35XX_RATE(24 * MHZ, 275000000, 275, 3, 3),
> >> +    PLL_35XX_RATE(24 * MHZ, 206000000, 206, 3, 3),
> >> +    PLL_35XX_RATE(24 * MHZ, 165000000, 110, 2, 3),
> >> +    PLL_35XX_RATE(24 * MHZ, 138000000, 184, 2, 4),
> >
> > Except for 825Mhz, I can't find the target frequency
> > on Exynos5422 TRM document. Usually, Exynos TRM specified
> > the supported stable clocks. It means that undefined clocks
> > are not stable as I knew. Where do you find them?
> >
> > When I calculated the PLL frequency with PMS value, it is correct.
> > But, just we need to check the reference of undefined clocks on TRM
> > in order to guarantee the stable operation.
> They values live in vendor code for Android.
> I have tested the DMC & DDR with these ratios in stress scenarios
> for a few days and it was stable.

If possible, please share the url of original vendor code.

>
> >
> > Remove 933/138Mhz because exynos5433-dmc.c doesn't use 933Mhz and 138Mh=
z
> > and also Exynos5422 TRM doesn't define 933/138Mhz on pll table.
> OK, I will remove them.
> >
> >> +};
> >> +
> >>   static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl=
[] =3D {
> >>      PLL_36XX_RATE(24 * MHZ, 600000000U, 100, 2, 1, 0),
> >>      PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0),
> >> @@ -1467,7 +1480,7 @@ static void __init exynos5x_clk_init(struct devi=
ce_node *np,
> >>              exynos5x_plls[apll].rate_table =3D exynos5420_pll2550x_24=
mhz_tbl;
> >>              exynos5x_plls[epll].rate_table =3D exynos5420_epll_24mhz_=
tbl;
> >>              exynos5x_plls[kpll].rate_table =3D exynos5420_pll2550x_24=
mhz_tbl;
> >> -            exynos5x_plls[bpll].rate_table =3D exynos5420_pll2550x_24=
mhz_tbl;
> >> +            exynos5x_plls[bpll].rate_table =3D exynos5422_bpll_rate_t=
able;
> >
> > Exynos5422 used the same PLL table for apll, kpll, bpll and so on.
> > You don't need to make the separate pll table. Just add new entries
> > to exynos5420_pll2550x_24mhz_tbl table.
> OK, I will extend the exynos5420_pll2550x_24mhz_tbl table.
>
> In v4 patch set, it will be fixed.
>
> Regards,
> Lukasz
> >
> >>      }
> >>
> >>      samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_=
plls),
> >>
> >


--
Best Regards,
Chanwoo Choi
Samsung Electronics