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[209.132.180.67]) by mx.google.com with ESMTP id k20si176922pfb.215.2019.02.04.06.38.47; Mon, 04 Feb 2019 06:39:02 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=UOMvXWSV; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731153AbfBDOAO (ORCPT + 99 others); Mon, 4 Feb 2019 09:00:14 -0500 Received: from mail.kernel.org ([198.145.29.99]:56664 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728977AbfBDOAN (ORCPT ); Mon, 4 Feb 2019 09:00:13 -0500 Received: from bbrezillon (unknown [91.160.177.164]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id BAB872082F; Mon, 4 Feb 2019 14:00:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1549288813; bh=rWhYzT7UjHT4ejUyjxjI9R2JCrNUWzH8DfYNDXDEMWQ=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=UOMvXWSVLM1sjqhzgedjrPZL37SAyM1KYnh7VZyQg2PSGoYC3sDIuu5cIEP1vQ9DR +fY4kuf+1qOBbEBxOmhTEaM/tCGhPUCcTc3iENUI8ThCz9bxr/07wH+/+oV5gD+5EF w/E25sENpGxO2KcI583sv9xwcFWozi2YpC8Gll5A= Date: Mon, 4 Feb 2019 15:00:05 +0100 From: Boris Brezillon To: Cc: , , , , , , , , , , , , Subject: Re: [PATCH v4 01/13] spi: atmel-quadspi: cache MR value to avoid a write access Message-ID: <20190204150005.3567bf29@bbrezillon> In-Reply-To: <20190204100910.26701-2-tudor.ambarus@microchip.com> References: <20190204100910.26701-1-tudor.ambarus@microchip.com> <20190204100910.26701-2-tudor.ambarus@microchip.com> X-Mailer: Claws Mail 3.16.0 (GTK+ 2.24.32; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 4 Feb 2019 10:09:22 +0000 wrote: > From: Tudor Ambarus > > Set the controller by default in Serial Memory Mode (SMM) at probe. > Cache Mode Register (MR) value to avoid write access when setting > the controller in serial memory mode at exec_op(). > > Signed-off-by: Tudor Ambarus Reviewed-by: Boris Brezillon > --- > v4: s/smm/mr, init controller in serial memory mode by default > v3: update smm value when different. rename mr/smm > v2: cache MR value instead of moving the write access at probe > > drivers/spi/atmel-quadspi.c | 14 +++++++++++++- > 1 file changed, 13 insertions(+), 1 deletion(-) > > diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c > index ddc712410812..d6864d29f294 100644 > --- a/drivers/spi/atmel-quadspi.c > +++ b/drivers/spi/atmel-quadspi.c > @@ -155,6 +155,7 @@ struct atmel_qspi { > struct clk *clk; > struct platform_device *pdev; > u32 pending; > + u32 mr; > struct completion cmd_completion; > }; > > @@ -238,7 +239,14 @@ static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) > icr = QSPI_ICR_INST(op->cmd.opcode); > ifr = QSPI_IFR_INSTEN; > > - qspi_writel(aq, QSPI_MR, QSPI_MR_SMM); > + /* > + * If the QSPI controller is set in regular SPI mode, set it in > + * Serial Memory Mode (SMM). > + */ > + if (aq->mr != QSPI_MR_SMM) { > + qspi_writel(aq, QSPI_MR, QSPI_MR_SMM); > + aq->mr = QSPI_MR_SMM; > + } > > mode = find_mode(op); > if (mode < 0) > @@ -381,6 +389,10 @@ static int atmel_qspi_init(struct atmel_qspi *aq) > /* Reset the QSPI controller */ > qspi_writel(aq, QSPI_CR, QSPI_CR_SWRST); > > + /* Set the QSPI controller by default in Serial Memory Mode */ > + qspi_writel(aq, QSPI_MR, QSPI_MR_SMM); > + aq->mr = QSPI_MR_SMM; > + > /* Enable the QSPI controller */ > qspi_writel(aq, QSPI_CR, QSPI_CR_QSPIEN); >