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received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: upDX6KtCRhe9Scv0Kb9+qW04jx6XjQWx4m638up9Z1PpoNKFdPVvzNJRzJa+zSDl97gVp3X9nUqUXL0cOTHuOvJhPGnQfxrbOuHURMEUK/zhrz52uHC3QcwOlKWwyeEwAeEBXMiU7xjENhgohxzRk9YdLtmukIw96XDPH5+MGFl5WIoF6WNjJwJ2Kv64FjQcSbjtdg6C6EJpiDLHq5hx+vBHzAlGpGz3m1Bbx/oDzTuhSFelFPjtSRp8Bw7j3e5o5lUCWnfkr1l2dxt41LazJM6xYzaG2qUGNKmCuhk3mk08O1mFcKbA/mKkN2D9LeZ/ijgG35viUmP4w7MGOi2+nuOioZ5YK4mUQfIdjvWGQAPLey+V230a/eaQXwVFPkLbp6HxjsfPQTQJ+5Qidju2R0YkGurCV+SHWRt3RXpqG44= Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3f642437-e0c3-4d0f-d257-08d68aaef331 X-MS-Exchange-CrossTenant-originalarrivaltime: 04 Feb 2019 14:42:08.7335 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3274 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org During AVIC temporary deactivation, guest could update APIC ID, DFR and LDR registers, which would not be trapped by avic_unaccelerated_ccess_interception(). In this case, we need to update the AVIC logical APIC ID table accordingly. Signed-off-by: Suravee Suthikulpanit --- arch/x86/kvm/svm.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c index 75508f665aef..c33f02b4a19e 100644 --- a/arch/x86/kvm/svm.c +++ b/arch/x86/kvm/svm.c @@ -4649,6 +4649,24 @@ static void avic_handle_dfr_update(struct kvm_vcpu *= vcpu) svm->dfr_reg =3D dfr; } =20 +static void svm_hwapic_ldr_update(struct kvm_vcpu *vcpu) +{ + if (svm_get_enable_apicv(vcpu) && !kvm_vcpu_apicv_active(vcpu)) + avic_handle_ldr_update(vcpu); +} + +static void svm_hwapic_apic_id_update(struct kvm_vcpu *vcpu) +{ + if (svm_get_enable_apicv(vcpu) && !kvm_vcpu_apicv_active(vcpu)) + avic_handle_apic_id_update(vcpu); +} + +static void svm_hwapic_dfr_update(struct kvm_vcpu *vcpu) +{ + if (svm_get_enable_apicv(vcpu) && !kvm_vcpu_apicv_active(vcpu)) + avic_handle_dfr_update(vcpu); +} + static int avic_unaccel_trap_write(struct vcpu_svm *svm) { struct kvm_lapic *apic =3D svm->vcpu.arch.apic; @@ -7166,6 +7184,9 @@ static struct kvm_x86_ops svm_x86_ops __ro_after_init= =3D { .load_eoi_exitmap =3D svm_load_eoi_exitmap, .hwapic_irr_update =3D svm_hwapic_irr_update, .hwapic_isr_update =3D svm_hwapic_isr_update, + .hwapic_apic_id_update =3D svm_hwapic_apic_id_update, + .hwapic_dfr_update =3D svm_hwapic_dfr_update, + .hwapic_ldr_update =3D svm_hwapic_ldr_update, .sync_pir_to_irr =3D kvm_lapic_find_highest_irr, .apicv_post_state_restore =3D avic_post_state_restore, =20 --=20 2.17.1