Received: by 2002:ac0:8c9a:0:0:0:0:0 with SMTP id r26csp4295219ima; Mon, 4 Feb 2019 13:50:32 -0800 (PST) X-Google-Smtp-Source: AHgI3Ian/rGo+WZ3h6hDdPtYToAHszB5WZbD3C617BjjpzLAXm5XYHNQ8W0+iup5qf82BpiOKm3R X-Received: by 2002:a17:902:5ac2:: with SMTP id g2mr1520365plm.313.1549317032886; Mon, 04 Feb 2019 13:50:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549317032; cv=none; d=google.com; s=arc-20160816; b=rWhgNQXfpecAQoYGOhFEFmamMxbTM3WbIexz3qNktVF+nWy7lPg0A5LmOeR6OoG55x lzYyBalBu4Vt9X2og4kwK9cRmN6+Jkeq28Cvfep0x4RIV2QqnNqaWvtnr8F+Qi3M/AuE El4Lj+zN96Z/nmgInohTRNy1ssFYpDnwCqboFi21FNrlxRrydJR80iVwT2gbiqdJ6jga cUlOM5LWbSBzLatR7eQy0ZzwYZrVqgLNqZSIkzbL0gnNK85zqxUMsFYNNbmukx3s7zAg W/myLkqOdi2d3ZJQh0xJR3TYxKUFpkDZr8eQjd1RF6emElu0OKMJp6jZeDYoRa0mzQV0 LPSA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from; bh=5WyaGzF2qcsfHXkNJT2TwcQk7JpjRJCsTjhADU8q+ow=; b=kJTvsdIKmuPKD+KY1Ep7mFq1mipIaAkf2kXTpNpYoKhEQBeOWa89o6nWfMwifsv97A bfjukk0yX8HeLUbgCL4CiRdqN6EHTqkySYfk6Zp14vVts4SnNVUyfc6OP/a1xGKZezDw 22UMJKvdfOEZ+rgzQpBzkjdqkqQs+LvmN0GL3D4JM4GLmyBDAqr9Mt4qpcvS6+NScbLT RbcalQ5T4eHurhSr8IgTYuecFckROABPDo8TRa1aNFY8lk7/PS4Aufqcblvjy9UQw3oU 940sTsefE9TcC9cpz92tbzTjNMjXv8LbP38iCmRFa02ReYaeiA9XqY+GdC6OQBbSxhf8 uZhg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e10si1028506pgc.113.2019.02.04.13.50.17; Mon, 04 Feb 2019 13:50:32 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729902AbfBDUma (ORCPT + 99 others); Mon, 4 Feb 2019 15:42:30 -0500 Received: from mga05.intel.com ([192.55.52.43]:31022 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729889AbfBDUm3 (ORCPT ); Mon, 4 Feb 2019 15:42:29 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 04 Feb 2019 12:42:28 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,560,1539673200"; d="scan'208";a="131064327" Received: from rchatre-s.jf.intel.com ([10.54.70.76]) by FMSMGA003.fm.intel.com with ESMTP; 04 Feb 2019 12:42:28 -0800 From: Reinette Chatre To: tglx@linutronix.de, fenghua.yu@intel.com, bp@alien8.de, tony.luck@intel.com Cc: gavin.hindman@intel.com, jithu.joseph@intel.com, mingo@redhat.com, hpa@zytor.com, x86@kernel.org, linux-kernel@vger.kernel.org, Reinette Chatre Subject: [PATCH] x86/resctrl: Remove duplicate MSR_MISC_FEATURE_CONTROL definition Date: Mon, 4 Feb 2019 12:41:36 -0800 Message-Id: X-Mailer: git-send-email 2.17.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The definition of MSR_MISC_FEATURE_CONTROL was first introduced in commit 98af74599ea0 ("x86 msr_index.h: Define MSR_MISC_FEATURE_CONTROL") and present in Linux since v4.11. The Cache Pseudo-Locking code added this duplicate definition in more recent commit f2a177292bd0 ("x86/intel_rdt: Discover supported platforms via prefetch disable bits"), available since v4.19. Remove the duplicate definition from the resctrl subsystem and let that code obtain the needed definition from the core architecture msr-index.h instead. Fixes: f2a177292bd0 ("x86/intel_rdt: Discover supported platforms via prefetch disable bits") Signed-off-by: Reinette Chatre --- arch/x86/kernel/cpu/resctrl/pseudo_lock.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c index 14bed6af8377..604c0e3bcc83 100644 --- a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c +++ b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c @@ -33,13 +33,6 @@ #define CREATE_TRACE_POINTS #include "pseudo_lock_event.h" -/* - * MSR_MISC_FEATURE_CONTROL register enables the modification of hardware - * prefetcher state. Details about this register can be found in the MSR - * tables for specific platforms found in Intel's SDM. - */ -#define MSR_MISC_FEATURE_CONTROL 0x000001a4 - /* * The bits needed to disable hardware prefetching varies based on the * platform. During initialization we will discover which bits to use. -- 2.17.0