Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
Subject: Re: [PATCH 07/35] ARM: davinci: aintc: use irq domain
To:     Bartosz Golaszewski <brgl@bgdev.pl>, Sekhar Nori <nsekhar@ti.com>,
        Kevin Hilman <khilman@kernel.org>,
        Thomas Gleixner <tglx@linutronix.de>,
        Jason Cooper <jason@lakedaemon.net>,
        Marc Zyngier <marc.zyngier@arm.com>
Cc:     Bartosz Golaszewski <bgolaszewski@baylibre.com>,
        linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org
References: <20190131133928.17985-1-brgl@bgdev.pl>
 <20190131133928.17985-8-brgl@bgdev.pl>
From:   David Lechner <david@lechnology.com>
Message-ID: <90995667-37cd-62a9-a40e-ee104016faf9@lechnology.com>
Date:   Mon, 4 Feb 2019 16:42:12 -0600
User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101
 Thunderbird/60.4.0
MIME-Version: 1.0
In-Reply-To: <20190131133928.17985-8-brgl@bgdev.pl>
Content-Type: text/plain; charset=utf-8; format=flowed
Content-Language: en-US
Content-Transfer-Encoding: 7bit
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk

On 1/31/19 7:39 AM, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> 
> We need to create an irq domain if we want to select SPARSE_IRQ. The
> cp-intc driver already supports it, but aintc doesn't. Use the helpers
> provided by the generic irq chip abstraction.
> 
> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> ---
>   arch/arm/mach-davinci/irq.c | 38 ++++++++++++++++++++++++++-----------
>   1 file changed, 27 insertions(+), 11 deletions(-)
> 
> diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c
> index e539bc65d4ef..c874ea269411 100644
> --- a/arch/arm/mach-davinci/irq.c
> +++ b/arch/arm/mach-davinci/irq.c
> @@ -23,6 +23,7 @@
>   #include <linux/interrupt.h>
>   #include <linux/irq.h>
>   #include <linux/io.h>
> +#include <linux/irqdomain.h>
>   
>   #include <mach/hardware.h>
>   #include <mach/cputype.h>
> @@ -43,6 +44,7 @@
>   #define IRQ_INTPRI7_REG_OFFSET	0x004C
>   
>   static void __iomem *davinci_intc_base;
> +static struct irq_domain *davinci_irq_domain;
>   
>   static inline void davinci_irq_writel(unsigned long value, int offset)
>   {
> @@ -55,17 +57,15 @@ static inline unsigned long davinci_irq_readl(int offset)
>   }
>   
>   static __init void
> -davinci_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
> +davinci_irq_setup_gc(void __iomem *base,
> +		     unsigned int irq_start, unsigned int num)
>   {
>   	struct irq_chip_generic *gc;
>   	struct irq_chip_type *ct;
>   
> -	gc = irq_alloc_generic_chip("AINTC", 1, irq_start, base, handle_edge_irq);
> -	if (!gc) {
> -		pr_err("%s: irq_alloc_generic_chip for IRQ %u failed\n",
> -		       __func__, irq_start);
> -		return;
> -	}
> +	gc = irq_get_domain_generic_chip(davinci_irq_domain, irq_start);

check for (gc == NULL) here?