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[209.132.180.67]) by mx.google.com with ESMTP id j10si3383158plg.123.2019.02.05.05.38.34; Tue, 05 Feb 2019 05:38:51 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729323AbfBENS6 convert rfc822-to-8bit (ORCPT + 99 others); Tue, 5 Feb 2019 08:18:58 -0500 Received: from relay10.mail.gandi.net ([217.70.178.230]:50337 "EHLO relay10.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726276AbfBENS6 (ORCPT ); Tue, 5 Feb 2019 08:18:58 -0500 Received: from xps13 (aaubervilliers-681-1-80-177.w90-88.abo.wanadoo.fr [90.88.22.177]) (Authenticated sender: miquel.raynal@bootlin.com) by relay10.mail.gandi.net (Postfix) with ESMTPSA id B7DB7240011; Tue, 5 Feb 2019 13:18:54 +0000 (UTC) Date: Tue, 5 Feb 2019 14:18:53 +0100 From: Miquel Raynal To: Boris Brezillon Cc: Dinh Nguyen , Richard Weinberger , Masahiro Yamada , Marek Vasut , Linux Kernel Mailing List , Boris Brezillon , linux-mtd , Brian Norris , David Woodhouse Subject: Re: [PATCH] mtd: rawnand: denali_dt: remove single anonymous clock support Message-ID: <20190205141853.4b7ed954@xps13> In-Reply-To: <20190131182644.366a54a5@bbrezillon> References: <1547539894-12898-1-git-send-email-yamada.masahiro@socionext.com> <20190115092229.59e09c2d@xps13> <20190128112007.440046e6@xps13> <20190131182644.366a54a5@bbrezillon> Organization: Bootlin X-Mailer: Claws Mail 3.17.1 (GTK+ 2.24.32; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Dinh, Boris Brezillon wrote on Thu, 31 Jan 2019 18:26:44 +0100: > Hi Dinh, > > On Thu, 31 Jan 2019 11:24:16 -0600 > Dinh Nguyen wrote: > > > On 1/28/19 4:20 AM, Miquel Raynal wrote: > > > Hi Dinh, > > > > > > Masahiro Yamada wrote on Wed, 16 Jan > > > 2019 10:27:11 +0900: > > > > > >> (+CC Dinh Nguyen) > > >> > > >> On Tue, Jan 15, 2019 at 5:22 PM Miquel Raynal wrote: > > >>> > > >>> Hi Masahiro, > > >>> > > >>> Masahiro Yamada wrote on Tue, 15 Jan > > >>> 2019 17:11:34 +0900: > > >>> > > >>>> Commit 6f1fe97bec34 ("mtd: rawnand: denali_dt: add more clocks based > > >>>> on IP datasheet") introduced a more correct binding that requires > > >>>> three named clocks. > > >>>> > > >>>> Now that all upstream DT files migrated over to it, remove the single > > >>>> anonymous clock support. > > >>> > > >>> I would love to do that but I think this is against the "DT backward > > >>> compatibility rule". > > >> > > >> Yeah, I know this rule, but we break DT binding from time to time. > > >> > > >> > > >> > > >>> Anyway, IIRC it is accepted that this kind of > > >>> rule might be broken if decided per the arch-maintainer (in this > > >>> case, you I suppose). So if this is really what you want, I'll queue > > >>> it. > > >> > > >> My platform is fine, but this driver is used by SOCFPGA boards as well. > > >> > > >> I CCed the SOCFPGA maintainer, Dinh Nguyen. > > >> > > > > > > Gentle ping on this topic. > > > > > > > This patch looks fine to be. Feel free to add: > > > > Tested-by: Dinh Nguyen > > I think Miquel is waiting for an Acked-by to confirm that you're okay > breaking backward compat with old DT. Yes, I am waiting for your Acked-by. Thanks, Miquèl