Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
MIME-Version: 1.0
References: <20190131133928.17985-1-brgl@bgdev.pl> <20190131133928.17985-6-brgl@bgdev.pl>
 <3038ba79-f411-9aa1-00ec-689060ed13d4@lechnology.com> <21c3d8cd-f767-04bc-f4d8-3001405ffd1d@ti.com>
In-Reply-To: <21c3d8cd-f767-04bc-f4d8-3001405ffd1d@ti.com>
From:   Bartosz Golaszewski <bgolaszewski@baylibre.com>
Date:   Wed, 6 Feb 2019 14:32:06 +0100
Message-ID: <CAMpxmJWU6WRK70xNN72Ke2kXi6F-uLWrCpF+K-+qKX3DcRy7uw@mail.gmail.com>
Subject: Re: [PATCH 05/35] ARM: davinci: drop irq defines from default_priorites
To:     Sekhar Nori <nsekhar@ti.com>
Cc:     David Lechner <david@lechnology.com>,
        Bartosz Golaszewski <brgl@bgdev.pl>,
        Kevin Hilman <khilman@kernel.org>,
        Thomas Gleixner <tglx@linutronix.de>,
        Jason Cooper <jason@lakedaemon.net>,
        Marc Zyngier <marc.zyngier@arm.com>,
        LKML <linux-kernel@vger.kernel.org>,
        arm-soc <linux-arm-kernel@lists.infradead.org>
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk

=C5=9Br., 6 lut 2019 o 14:03 Sekhar Nori <nsekhar@ti.com> napisa=C5=82(a):
>
> On 05/02/19 3:51 AM, David Lechner wrote:
> > On 1/31/19 7:38 AM, Bartosz Golaszewski wrote:
> >> From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> >>
> >> In order to select SPARSE_IRQ we need to make the interrupt numbers
> >> dynamic (at least at build-time for the top-level controller). The
> >> interrupt numbers are used as array indexes for irq priorities.
> >>
> >> Drop the defines and just initialize the arrays in a linear manner.
> >>
> >> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> >> ---
> >
> > ...
> >
> >> -static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] =3D {
> >> -    [IRQ_DM355_CCDC_VDINT0]        =3D 2,
> >> -    [IRQ_DM355_CCDC_VDINT1]        =3D 6,
> >> -    [IRQ_DM355_CCDC_VDINT2]        =3D 6,
> >> -    [IRQ_DM355_IPIPE_HST]        =3D 6,
> >> -    [IRQ_DM355_H3AINT]        =3D 6,
> >> -    [IRQ_DM355_IPIPE_SDR]        =3D 6,
> >> -    [IRQ_DM355_IPIPEIFINT]        =3D 6,
> >> -    [IRQ_DM355_OSDINT]        =3D 7,
> >> -    [IRQ_DM355_VENCINT]        =3D 6,
> >> -    [IRQ_ASQINT]            =3D 6,
> >> -    [IRQ_IMXINT]            =3D 6,
> >> -    [IRQ_USBINT]            =3D 4,
> >> -    [IRQ_DM355_RTOINT]        =3D 4,
> >> -    [IRQ_DM355_UARTINT2]        =3D 7,
> >> -    [IRQ_DM355_TINT6]        =3D 7,
> >> -    [IRQ_CCINT0]            =3D 5,    /* dma */
> >> -    [IRQ_CCERRINT]            =3D 5,    /* dma */
> >> -    [IRQ_TCERRINT0]            =3D 5,    /* dma */
> >> -    [IRQ_TCERRINT]            =3D 5,    /* dma */
> >> -    [IRQ_DM355_SPINT2_1]        =3D 7,
> >> -    [IRQ_DM355_TINT7]        =3D 4,
> >> -    [IRQ_DM355_SDIOINT0]        =3D 7,
> >> -    [IRQ_MBXINT]            =3D 7,
> >> -    [IRQ_MBRINT]            =3D 7,
> >> -    [IRQ_MMCINT]            =3D 7,
> >> -    [IRQ_DM355_MMCINT1]        =3D 7,
> >> -    [IRQ_DM355_PWMINT3]        =3D 7,
> >> -    [IRQ_DDRINT]            =3D 7,
> >> -    [IRQ_AEMIFINT]            =3D 7,
> >> -    [IRQ_DM355_SDIOINT1]        =3D 4,
> >> -    [IRQ_TINT0_TINT12]        =3D 2,    /* clockevent */
> >> -    [IRQ_TINT0_TINT34]        =3D 2,    /* clocksource */
> >> -    [IRQ_TINT1_TINT12]        =3D 7,    /* DSP timer */
> >> -    [IRQ_TINT1_TINT34]        =3D 7,    /* system tick */
> >> -    [IRQ_PWMINT0]            =3D 7,
> >> -    [IRQ_PWMINT1]            =3D 7,
> >> -    [IRQ_PWMINT2]            =3D 7,
> >> -    [IRQ_I2C]            =3D 3,
> >> -    [IRQ_UARTINT0]            =3D 3,
> >> -    [IRQ_UARTINT1]            =3D 3,
> >> -    [IRQ_DM355_SPINT0_0]        =3D 3,
> >> -    [IRQ_DM355_SPINT0_1]        =3D 3,
> >> -    [IRQ_DM355_GPIO0]        =3D 3,
> >> -    [IRQ_DM355_GPIO1]        =3D 7,
> >> -    [IRQ_DM355_GPIO2]        =3D 4,
> >> -    [IRQ_DM355_GPIO3]        =3D 4,
> >> -    [IRQ_DM355_GPIO4]        =3D 7,
> >> -    [IRQ_DM355_GPIO5]        =3D 7,
> >> -    [IRQ_DM355_GPIO6]        =3D 7,
> >> -    [IRQ_DM355_GPIO7]        =3D 7,
> >> -    [IRQ_DM355_GPIO8]        =3D 7,
> >> -    [IRQ_DM355_GPIO9]        =3D 7,
> >> -    [IRQ_DM355_GPIOBNK0]        =3D 7,
> >> -    [IRQ_DM355_GPIOBNK1]        =3D 7,
> >> -    [IRQ_DM355_GPIOBNK2]        =3D 7,
> >> -    [IRQ_DM355_GPIOBNK3]        =3D 7,
> >> -    [IRQ_DM355_GPIOBNK4]        =3D 7,
> >> -    [IRQ_DM355_GPIOBNK5]        =3D 7,
> >> -    [IRQ_DM355_GPIOBNK6]        =3D 7,
> >> -    [IRQ_COMMTX]            =3D 7,
> >> -    [IRQ_COMMRX]            =3D 7,
> >> -    [IRQ_EMUINT]            =3D 7,
> >> +static u8 dm355_aintc_prios[] =3D {
> >> +    2, 6, 6, 6, 6, 6, 6, 7,
> >> +    6, 6, 6, 4, 4, 7, 7, 5,
> >> +    5, 5, 5, 7, 4, 7, 7, 7,
> >> +    7, 7, 7, 7, 7, 4, 2, 2,
> >> +    7, 7, 7, 7, 7, 3, 3, 3,
> >> +    3, 3, 3, 7, 4, 4, 7, 7,
> >> +    7, 7, 7, 7, 7, 7, 7, 7,
> >> +    7, 7, 7, 7, 7, 7, 0, 0,
> >>   };
> >
> > Hmm... this makes it harder to see what is going on here.
> > You can no longer see which priority corresponds to which
> > IRQ without consulting a manual.
>
> I agree with David here. The interrupt numbers are dynamic, but the
> interrupt number offset from hardware point-of-view is fixed. So can
> these macros be re-purposed to represent the hardware offset (eventually
> you would pass them to DAVINCI_INTC_IRQ())?
>
> Thanks,
> Sekhar

Should we keep the mach/irqs.h header then? While working on patches
for supporting the multi_v5_defconfig build I noticed the mach/*
headers tend to cause build problems in certain drivers that use them.
Most machines have gotten rid of them. Should we maybe create a local
header in mach-davinci/?

Bart