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[209.132.180.67]) by mx.google.com with ESMTP id h13si5883443pgs.17.2019.02.06.10.00.04; Wed, 06 Feb 2019 10:00:20 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SCvzvdVO; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730311AbfBFRX1 (ORCPT + 99 others); Wed, 6 Feb 2019 12:23:27 -0500 Received: from mail-ed1-f67.google.com ([209.85.208.67]:35441 "EHLO mail-ed1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727467AbfBFRX1 (ORCPT ); Wed, 6 Feb 2019 12:23:27 -0500 Received: by mail-ed1-f67.google.com with SMTP id b17so2411413eds.2 for ; Wed, 06 Feb 2019 09:23:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=JvcKwIWlny3ttJZ1xLAWt497mnvC18dJy450P90yM2w=; b=SCvzvdVOhvlAy67voL7FYAvyuejhJl4vSCGdpxJlOMsY+8wabGiSJZA1uUaEPZSzJz 6TsIIgrJRKv/aNHU8vW8J4FSe1X/Xw6iDZGBqG5c9rNEd3BJoQQdQNmcLBMKscJmUJ7b 4Z10Md+g3Fr53D5TOrI3G/vYYXS+OP3EFKsm48qVNtslHNlAiWabEvqagd43sg8AF2q3 L+kGfJBklnwUrC2dsnIJdEFK79ARloXzeMalaaUpT1yxSYeZtxYpLj6STdegY+D3w6wa 0AbFdVPqaCQaS+PpizEmsAudri2P7nzy7+k9j/2bfYw1FnGwmkdaoZAXYxcVWAk7nYqB TLZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=JvcKwIWlny3ttJZ1xLAWt497mnvC18dJy450P90yM2w=; b=bCX+WmXJoh+2FXHOi76xZk2SbjPiyPuR/+fTlhSUc/qGVXawyHdLkpfeto3qZqkida my8jbWHw/TWkP4JiYNn99pFV3gPrljHwL8/fnx/B0UX6viCG14A9sNIMtqwNUZ7vY53u VUfSdpicE52nilZg09Zl6lvK8aDSegcc35pnR5UPpMmDQqG/naJ1TDcv7J2VUxOoFrFu VgO8eqbJeFyrHmRyuPl5IZqUWHtvLCDMB6/oMR8GnGkiz5qbBqcKWX96yQOeetui03Ij 8jwe81YIJi7QWl/w2He8G8gOcmnWMnXv1RoPqmRZEyypKT8Zz100sXprvMhu2Yli+NnZ uOoA== X-Gm-Message-State: AHQUAuaPNYYv89jzEaIBdJrNV3NS5Sfu8CcitJanVzMxVzMwxeFzfmdJ 56fvNQDOqOe/2iK60nVNyGMburHrBw3qpz+cYmI4Ew== X-Received: by 2002:a17:906:b38a:: with SMTP id o10mr3789264ejz.217.1549473804836; Wed, 06 Feb 2019 09:23:24 -0800 (PST) MIME-Version: 1.0 References: <20190124120658.30288-1-ard.biesheuvel@linaro.org> <3cca35a9-c71c-a100-b29d-31ba0d1d10b1@amd.com> <961e758d-b0a0-8f6c-a8fa-c3047e058706@gmail.com> In-Reply-To: From: Ard Biesheuvel Date: Wed, 6 Feb 2019 17:23:13 +0000 Message-ID: Subject: Re: [PATCH] drm: enable uncached DMA optimization for ARM and arm64 To: "Koenig, Christian" Cc: Alex Deucher , "Daenzer, Michel" , Carsten Haitzler , Maxime Ripard , "linux-kernel@vger.kernel.org" , dri-devel , "Zhang, Jerry" , Christoph Hellwig , David Airlie , "Huang, Ray" , amd-gfx list , Michael Ellerman , Will Deacon , "Deucher, Alexander" , Sean Paul , "linux-arm-kernel@lists.infradead.org" , Robin Murphy Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 25 Jan 2019 at 11:35, Ard Biesheuvel wr= ote: > > On Fri, 25 Jan 2019 at 12:30, Christian K=C3=B6nig > wrote: > > > > Am 25.01.19 um 09:43 schrieb Ard Biesheuvel: > > > On Thu, 24 Jan 2019 at 15:01, Alex Deucher wr= ote: > > >> On Thu, Jan 24, 2019 at 9:00 AM Ard Biesheuvel > > >> wrote: > > >>> On Thu, 24 Jan 2019 at 13:31, Koenig, Christian > > >>> wrote: > > >>>> Am 24.01.19 um 13:06 schrieb Ard Biesheuvel: > > >>>>> The DRM driver stack is designed to work with cache coherent devi= ces > > >>>>> only, but permits an optimization to be enabled in some cases, wh= ere > > >>>>> for some buffers, both the CPU and the GPU use uncached mappings, > > >>>>> removing the need for DMA snooping and allocation in the CPU cach= es. > > >>>>> > > >>>>> The use of uncached GPU mappings relies on the correct implementa= tion > > >>>>> of the PCIe NoSnoop TLP attribute by the platform, otherwise the = GPU > > >>>>> will use cached mappings nonetheless. On x86 platforms, this does= not > > >>>>> seem to matter, as uncached CPU mappings will snoop the caches in= any > > >>>>> case. However, on ARM and arm64, enabling this optimization on a > > >>>>> platform where NoSnoop is ignored results in loss of coherency, w= hich > > >>>>> breaks correct operation of the device. Since we have no way of > > >>>>> detecting whether NoSnoop works or not, just disable this > > >>>>> optimization entirely for ARM and arm64. > > >>>>> > > >>>>> Cc: Christian Koenig > > >>>>> Cc: Alex Deucher > > >>>>> Cc: David Zhou > > >>>>> Cc: Huang Rui > > >>>>> Cc: Junwei Zhang > > >>>>> Cc: Michel Daenzer > > >>>>> Cc: David Airlie > > >>>>> Cc: Daniel Vetter > > >>>>> Cc: Maarten Lankhorst > > >>>>> Cc: Maxime Ripard > > >>>>> Cc: Sean Paul > > >>>>> Cc: Michael Ellerman > > >>>>> Cc: Benjamin Herrenschmidt > > >>>>> Cc: Will Deacon > > >>>>> Cc: Christoph Hellwig > > >>>>> Cc: Robin Murphy > > >>>>> Cc: amd-gfx list > > >>>>> Cc: dri-devel > > >>>>> Reported-by: Carsten Haitzler > > >>>>> Signed-off-by: Ard Biesheuvel > > >>>> The subject line should probably read "disable uncached...". > > >>>> > > >>> Ugh, of course ... > > >>> > > >>>> With that fixed the patch is Reviewed-by: Christian K=C3=B6nig > > >>>> . > > >>>> > > >> Same: > > >> Reviewed-by: Alex Deucher > > >> > > > Thanks all > > > > > > Should I resend the patch with the subject corrected? > > > > I will update the subject line and push it upstream through > > drm-misc-next if nobody objects. > > > > Wonderful, thanks. Hi Christian, Are you still planning to merge this for v5.1? Thanks, Ard.