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[209.132.180.67]) by mx.google.com with ESMTP id x38si8394767pgl.419.2019.02.07.01.53.16; Thu, 07 Feb 2019 01:53:31 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726930AbfBGJuE (ORCPT + 99 others); Thu, 7 Feb 2019 04:50:04 -0500 Received: from relay11.mail.gandi.net ([217.70.178.231]:54241 "EHLO relay11.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726186AbfBGJuB (ORCPT ); Thu, 7 Feb 2019 04:50:01 -0500 Received: from mc-bl-xps13.lan (aaubervilliers-681-1-80-177.w90-88.abo.wanadoo.fr [90.88.22.177]) (Authenticated sender: maxime.chevallier@bootlin.com) by relay11.mail.gandi.net (Postfix) with ESMTPSA id DD84510001C; Thu, 7 Feb 2019 09:49:56 +0000 (UTC) From: Maxime Chevallier To: davem@davemloft.net Cc: Maxime Chevallier , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Andrew Lunn , Florian Fainelli , Heiner Kallweit , Russell King , linux-arm-kernel@lists.infradead.org, Antoine Tenart , thomas.petazzoni@bootlin.com, gregory.clement@bootlin.com, miquel.raynal@bootlin.com, nadavh@marvell.com, stefanc@marvell.com, mw@semihalf.com Subject: [PATCH net-next v2 01/10] net: phy: Update PHY linkmodes after config_init Date: Thu, 7 Feb 2019 10:49:30 +0100 Message-Id: <20190207094939.27369-2-maxime.chevallier@bootlin.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190207094939.27369-1-maxime.chevallier@bootlin.com> References: <20190207094939.27369-1-maxime.chevallier@bootlin.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org We want to be able to update a PHY's supported list in the config_init callback, so move the Pause parameters settings from phydrv->features after calling config_init to make sure these parameters aren't overwritten. Signed-off-by: Maxime Chevallier --- drivers/net/phy/phy_device.c | 89 +++++++++++++++++++++++------------- 1 file changed, 58 insertions(+), 31 deletions(-) diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c index 891e0178b97f..18a10565efd4 100644 --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c @@ -1059,6 +1059,59 @@ static int phy_poll_reset(struct phy_device *phydev) return 0; } +/** + * phy_update_linkmodes - Update and sanitize linkmodes and pause parameters + * @phydev: The PHY device whose parameters we want to update. + * + * Description: The list of supported and advertised linkmodes is not + * straightforward to maintain, since PHYs and MACs are subject to quirks and + * erratas. This function re-builds the list of the supported pause parameters + * by taking into account the parameters expressed in the driver's features + * list. + */ +static void phy_update_linkmodes(struct phy_device *phydev) +{ + struct device_driver *drv = phydev->mdio.dev.driver; + struct phy_driver *phydrv = to_phy_driver(drv); + + mutex_lock(&phydev->lock); + + /* The Pause Frame bits indicate that the PHY can support passing + * pause frames. During autonegotiation, the PHYs will determine if + * they should allow pause frames to pass. The MAC driver should then + * use that result to determine whether to enable flow control via + * pause frames. + * + * Normally, PHY drivers should not set the Pause bits, and instead + * allow phylib to do that. However, there may be some situations + * (e.g. hardware erratum) where the driver wants to set only one + * of these bits. + */ + if (test_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydrv->features) || + test_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydrv->features)) { + linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, + phydev->supported); + linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, + phydev->supported); + if (test_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydrv->features)) + linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, + phydev->supported); + if (test_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, + phydrv->features)) + linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, + phydev->supported); + } else { + linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, + phydev->supported); + linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, + phydev->supported); + } + + linkmode_copy(phydev->advertising, phydev->supported); + + mutex_unlock(&phydev->lock); +} + int phy_init_hw(struct phy_device *phydev) { int ret = 0; @@ -1082,6 +1135,11 @@ int phy_init_hw(struct phy_device *phydev) if (phydev->drv->config_init) ret = phydev->drv->config_init(phydev); + /* Update and sanitize the supported and advertised linkmodes, since + * they might have been changed in config_init + */ + phy_update_linkmodes(phydev); + return ret; } EXPORT_SYMBOL(phy_init_hw); @@ -2221,37 +2279,6 @@ static int phy_probe(struct device *dev) */ of_set_phy_eee_broken(phydev); - /* The Pause Frame bits indicate that the PHY can support passing - * pause frames. During autonegotiation, the PHYs will determine if - * they should allow pause frames to pass. The MAC driver should then - * use that result to determine whether to enable flow control via - * pause frames. - * - * Normally, PHY drivers should not set the Pause bits, and instead - * allow phylib to do that. However, there may be some situations - * (e.g. hardware erratum) where the driver wants to set only one - * of these bits. - */ - if (test_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydrv->features) || - test_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydrv->features)) { - linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, - phydev->supported); - linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, - phydev->supported); - if (test_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydrv->features)) - linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, - phydev->supported); - if (test_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, - phydrv->features)) - linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, - phydev->supported); - } else { - linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, - phydev->supported); - linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, - phydev->supported); - } - /* Set the state to READY by default */ phydev->state = PHY_READY; -- 2.19.2