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Subject: Re: [PATCH 02/35] ARM: davinci: select GENERIC_IRQ_MULTI_HANDLER
To:     Bartosz Golaszewski <brgl@bgdev.pl>
CC:     Kevin Hilman <khilman@kernel.org>,
        Thomas Gleixner <tglx@linutronix.de>,
        Jason Cooper <jason@lakedaemon.net>,
        Marc Zyngier <marc.zyngier@arm.com>,
        Linux ARM <linux-arm-kernel@lists.infradead.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        Bartosz Golaszewski <bgolaszewski@baylibre.com>
References: <20190131133928.17985-1-brgl@bgdev.pl>
 <20190131133928.17985-3-brgl@bgdev.pl>
 <eb09a892-d965-3ee2-dfe7-2dcbbcb03791@ti.com>
 <CAMRc=Me9gqfN6WuWPZ61M2pNC+ZrhxAX_=BzAr4_zxnfdL4G7Q@mail.gmail.com>
From:   Sekhar Nori <nsekhar@ti.com>
Message-ID: <7f5206ea-ad18-86c2-f9f0-3fccaf4932e9@ti.com>
Date:   Fri, 8 Feb 2019 14:29:43 +0530
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On 07/02/19 9:19 PM, Bartosz Golaszewski wrote:

>>> +static asmlinkage void __exception_irq_entry
>>> +cp_intc_handle_irq(struct pt_regs *regs)
>>> +{
>>> +     int irqnr = cp_intc_read(CP_INTC_PRIO_IDX);
>>> +
>>> +     irqnr &= 0xff;
>>> +
>>> +     handle_domain_irq(cp_intc_domain, irqnr, regs);
>>
>> This leaves out spurious interrupt handling present in existing assembly
>> code. Can you add it back. May be use omap_intc_handle_irq() as an
>> example for handling spurious IRQs.
>>
> 
> Hi Sekhar,
> 
> I started looking at this one and noticed that the manual says
> PRI_INDX field in the GPIR register is in bits 0-9 (mask 0x3ff) while
> the assembly logically ANDs it with 0xff. I guess it's because there
> can be no more interrupts than 255 but I'd at least explain it in a
> comment. Or should we use the proper mask? What do you think?

I think using mask 0x3ff to match TRM is fine.

Thanks,
Sekhar