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client-ip=188.184.36.46; helo=cernmxgwlb4.cern.ch; Received: from cernmxgwlb4.cern.ch (188.184.36.46) by HE1EUR02FT025.mail.protection.outlook.com (10.152.10.79) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.1580.10 via Frontend Transport; Mon, 11 Feb 2019 08:20:51 +0000 Received: from cernfe02.cern.ch (188.184.36.47) by cernmxgwlb4.cern.ch (188.184.36.46) with Microsoft SMTP Server (TLS) id 14.3.408.0; Mon, 11 Feb 2019 09:20:33 +0100 Received: from pcbe13614.localnet (2001:1458:202:121::100:40) by smtp.cern.ch (2001:1458:201:66::100:14) with Microsoft SMTP Server (TLS) id 14.3.408.0; Mon, 11 Feb 2019 09:20:32 +0100 From: Federico Vaga To: Andrew Lunn Reply-To: CC: Peter Korsgaard , , Subject: Re: [PATCH v3 3/5] i2c:ocores: add polling interface Date: Mon, 11 Feb 2019 09:20:32 +0100 Message-ID: <1894984.UOdFTssdus@pcbe13614> In-Reply-To: <20190209213353.GA9061@lunn.ch> References: <20190208161201.7860-1-federico.vaga@cern.ch> <20190208161201.7860-4-federico.vaga@cern.ch> <20190209213353.GA9061@lunn.ch> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; 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> > + int err; > > + > > + if (i2c->state == STATE_DONE || i2c->state == STATE_ERROR) { > > + /* transfer is over */ > > + mask = OCI2C_STAT_BUSY; > > + } else { > > + /* on going transfer */ > > + mask = OCI2C_STAT_TIP; > > + udelay((8 * 1000) / i2c->bus_clock_khz); > > + } > > + > > + /* > > + * once we are here we expect to get the expected result immediately > > + * so if after 1ms we timeout then something is broken. > > + */ > > + err = ocores_wait(i2c, OCI2C_STATUS, mask, 0, msecs_to_jiffies(1)); > > Hi Federico > > I did some timing tests for this. On my box, we request a udelay of > 80uS. The kernel actually delays for about 79uS. We then spin in > ocores_wait() for an additional 10-11uS, which is 3 to 4 iterations. > > There are actually 9 bits on the wire, not 8, since there is an > ACK/NACK bit after the actual data transfer. So i changed the delay to > (9 * 1000) / i2c->bus_clock_khz. That resulted in ocores_wait() mostly > not looping at all. But for reading an 4K AT24 EEPROM, it increased > the read time by 10ms, from 424ms to 434ms. So we should probably keep > with 8. > > Tested-by: Andrew Lunn I had a similar experience. I will add a comment in the code to explain that 8 is not a mistake but a conscious decision. Then I will add what you wrote here in the patch changelog > > Andrew