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[209.132.180.67]) by mx.google.com with ESMTP id m7si8843924pgi.547.2019.02.11.00.51.25; Mon, 11 Feb 2019 00:51:41 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727255AbfBKIuq (ORCPT + 99 others); Mon, 11 Feb 2019 03:50:46 -0500 Received: from foss.arm.com ([217.140.101.70]:44062 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726358AbfBKIup (ORCPT ); Mon, 11 Feb 2019 03:50:45 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B8FD480D; Mon, 11 Feb 2019 00:50:44 -0800 (PST) Received: from big-swifty.misterjones.org (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id EF2233F575; Mon, 11 Feb 2019 00:50:36 -0800 (PST) Date: Mon, 11 Feb 2019 08:50:27 +0000 Message-ID: <868symu2ss.wl-marc.zyngier@arm.com> From: Marc Zyngier To: Seiya Wang Cc: Matthias Brugger , Erin Lo , Rob Herring , Mark Rutland , "Thomas Gleixner" , Jason Cooper , "Greg Kroah-Hartman" , Stephen Boyd , , srv_heupstream , , , , , , , , Subject: Re: [PATCH v6 1/6] irqchip/mtk-sysirq: support 4 interrupt parameters for sysirq In-Reply-To: <1549866929.22817.20.camel@mtksdccf07> References: <1548317240-44682-1-git-send-email-erin.lo@mediatek.com> <1548317240-44682-2-git-send-email-erin.lo@mediatek.com> <898ca3d9-002b-e28e-fc97-86bc2538e9de@gmail.com> <626b5b46-aac7-1532-386e-2fed85bf4ad9@arm.com> <1549866929.22817.20.camel@mtksdccf07> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL/10.8 EasyPG/1.0.0 Emacs/25.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Organization: ARM Ltd MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 11 Feb 2019 06:35:29 +0000, Seiya Wang wrote: > > On Thu, 2019-02-07 at 15:52 +0000, Marc Zyngier wrote: > > On 07/02/2019 15:47, Marc Zyngier wrote: > > > On 07/02/2019 15:20, Matthias Brugger wrote: > > >> > > >> > > >> On 24/01/2019 09:07, Erin Lo wrote: > > >>> From: Seiya Wang > > >>> > > >>> To support partitioned PPIs, 4 interrupt parameters should be valid > > >>> for sysirq. > > >>> > > >>> Signed-off-by: Seiya Wang > > >>> Signed-off-by: Erin Lo > > >>> --- > > >>> drivers/irqchip/irq-mtk-sysirq.c | 4 ++-- > > >>> 1 file changed, 2 insertions(+), 2 deletions(-) > > >>> > > >>> diff --git a/drivers/irqchip/irq-mtk-sysirq.c b/drivers/irqchip/irq-mtk-sysirq.c > > >>> index 90aaf19..282736a 100644 > > >>> --- a/drivers/irqchip/irq-mtk-sysirq.c > > >>> +++ b/drivers/irqchip/irq-mtk-sysirq.c > > >>> @@ -81,7 +81,7 @@ static int mtk_sysirq_domain_translate(struct irq_domain *d, > > >>> unsigned int *type) > > >>> { > > >>> if (is_of_node(fwspec->fwnode)) { > > >>> - if (fwspec->param_count != 3) > > >>> + if (fwspec->param_count != 3 && fwspec->param_count != 4) > > >> > > >> Where is this 4th parameter used? > > > > > > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt#n14 > > Sorry, I fired Send way too early. > > > > What I wanted to add is that it is not clear to me why this change would > > be required here, as this driver only supports SPIs. It could be fixed > > by just relaxing the binding itself. > > > > Thanks, > > > > M. > > Do you mean that we should change #interrupt-cells back to 3 for sysirq > and remove the 4th parameters of every spi interrupts in mt8183.dtsi > (i.e. 3 parameters for spi, 4 for ppi) such that we can discard this > patch? It is more subtle than that: - PPIs must have the affinity parameter in their int-spec (since you need that for the PMU) - SPIs that are directly routed to the GIC must also have the affinity parameter (although set to zero). - SPIs that are routed via the sysirq block (or any other) can use the 3 parameter variant, as they are not resolved in the context of the GIC, but in that of the sysirq. But in short, yes. You should be able to drop this patch altogether. > If yes, we may need some time to verify the change before resending the > patch. That's absolutely fine. Thanks, M. -- Jazz is not dead, it just smell funny.