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[209.85.208.171]) by smtp.gmail.com with ESMTPSA id m10-v6sm2367755ljj.34.2019.02.11.14.34.48 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 11 Feb 2019 14:34:48 -0800 (PST) Received: by mail-lj1-f171.google.com with SMTP id j13-v6so494018ljc.2 for ; Mon, 11 Feb 2019 14:34:48 -0800 (PST) X-Received: by 2002:a2e:880a:: with SMTP id x10-v6mr321289ljh.174.1549924487924; Mon, 11 Feb 2019 14:34:47 -0800 (PST) MIME-Version: 1.0 References: <20190211172948.3322-1-will.deacon@arm.com> In-Reply-To: <20190211172948.3322-1-will.deacon@arm.com> From: Linus Torvalds Date: Mon, 11 Feb 2019 14:34:31 -0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [RFC PATCH] docs/memory-barriers.txt: Rewrite "KERNEL I/O BARRIER EFFECTS" section To: Will Deacon Cc: linux-arch , Linux List Kernel Mailing , "Paul E. McKenney" , Benjamin Herrenschmidt , Arnd Bergmann , Peter Zijlstra , Andrea Parri , Daniel Lustig , David Howells , Alan Stern Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Feb 11, 2019 at 9:30 AM Will Deacon wrote: > > + > + 1. All readX() and writeX() accesses to the same peripheral are ordered > + with respect to each other. For example, this ensures that MMIO register > + writes by the CPU to a particular device will arrive in program order. Hmm. I'd like more people look at strengthening this one wrt across CPUs and locking. Right now we document mmiowb(), but that "documentation" is really just a fairy tale. Very *very* few drivers actually do mmiowb() on their own. IOW, we should seriously just consider making the rule be that locking will order mmio too. Because that's practically the rule anyway. Powerpc already does it. IO within a locked region will serialize with the lock. Linus