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[209.132.180.67]) by mx.google.com with ESMTP id i14si8432301pfj.246.2019.02.11.18.58.10; Mon, 11 Feb 2019 18:58:26 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728034AbfBLC5l (ORCPT + 99 others); Mon, 11 Feb 2019 21:57:41 -0500 Received: from mailgw02.mediatek.com ([1.203.163.81]:17796 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726226AbfBLC5j (ORCPT ); Mon, 11 Feb 2019 21:57:39 -0500 X-UUID: bb7269ae5b2e448cb2887dddc754df06-20190212 X-UUID: bb7269ae5b2e448cb2887dddc754df06-20190212 Received: from mtkcas34.mediatek.inc [(172.27.4.250)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 1824614225; Tue, 12 Feb 2019 10:57:31 +0800 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by MTKMBS31DR.mediatek.inc (172.27.6.102) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 12 Feb 2019 10:57:29 +0800 Received: from [10.17.3.153] (10.17.3.153) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 12 Feb 2019 10:57:29 +0800 Message-ID: <1549940249.4980.56.camel@mhfsdcap03> Subject: Re: [RFC PATCH] PCI/portdrv: Support for subtractive decode bridge From: Honghui Zhang To: Bjorn Helgaas CC: , , , , , , , , , , , Date: Tue, 12 Feb 2019 10:57:29 +0800 In-Reply-To: <20190207151816.GI7268@google.com> References: <1544758829-10327-1-git-send-email-honghui.zhang@mediatek.com> <20190207151816.GI7268@google.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.2.3-0ubuntu6 Content-Transfer-Encoding: 7bit MIME-Version: 1.0 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 2019-02-07 at 09:18 -0600, Bjorn Helgaas wrote: > Hi Honghui, > > On Fri, Dec 14, 2018 at 11:40:29AM +0800, honghui.zhang@mediatek.com wrote: > > From: Honghui Zhang > > > > The Class Code for subtractive decode PCI-to-PCI bridge is 060401h, > > change the class_mask values to make portdrv support this type bridge. > > I assume you have a Root Port or Switch Port that supports subtractive > decode? I'm trying to understand how such a device would work. > Hi, Bjorn, Yes, most of Mediatek's RC device have set the class type as 060401h as HW default values, include mt2712 and mt7622. Those RC device work fine with all I have tried EP device except that the portdrv was not attached to those device. But no scenario need those service as far as I know. > Out of curiosity, can you show the "lspci -vv" output for the device > and the downstream devices of interest? > lspci only read the class type 0604h, it does not care about the subordinate values of the class type. I will put the "lspci -vv" output at bottom of this mail. > Do you happen to know whether this functionality is configurable, > e.g., is there some way software can enable or disable subtractive > decode? I assume this would be some device-specific thing, because I > can't find anything in the Bridge Control register or similar. The > PCIe spec doesn't even contain the word "subtractive". > Those class type values for Mediatek's RC has a register which could be used to change its values. We never touch this backdoor register since without the portdrv attached is fine, nobody ask for the port service yet. I did some homework for the subtractive decode PCI-to-PCI bridge, and did not found much more information about that. I guess those port service should also support subtractive bridge since spec does not forbidden that. > The "PCI Express to PCI/PCI-X Bridge Specification", r1.0, says a PCI > Express bridge (which would include Root Ports and Switch Ports) has a > Class Code of 0x060400 (Non-Subtractive PCI-PCI Bridge) (sec 1.1). > > Sec 1.3.4 says subtractive decode on the primary interface is "not > applicable or outside the scope of this spec". > > Bjorn > # lspci -vvv 00:01.0 Class 0604: Device 14c3:5396 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- (64-bit, prefetchable) Bus: primary=00, secondary=01, subordinate=01, sec-latency=64 I/O behind bridge: 00000000-00000fff Memory behind bridge: 20000000-206fffff Prefetchable memory behind bridge: 00000000-000fffff Secondary status: 66MHz+ FastB2B- ParErr- DEVSEL=slow >TAbort- Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [50] MSI: Enable+ Count=1/1 Maskable- 64bit+ Address: 000000000807a0c0 Data: 0000 Capabilities: [78] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- Capabilities: [80] Express (v2) Root Port (Slot+), MSI 01 DevCap: MaxPayload 256 bytes, PhantFunc 0 ExtTag- RBE+ DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend+ LnkCap: Port #1, Speed 5GT/s, Width x2, ASPM L0s L1, Exit Latency L0s <64ns, L1 <2us ClockPM- Surprise- LLActRep- BwNot+ ASPMOptComp+ LnkCtl: ASPM L1 Enabled; RCB 128 bytes Disabled- CommClk + ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise- Slot #0, PowerLimit 0.000W; Interlock- NoCompl+ SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- Changed: MRL- PresDet- LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Not Supported, TimeoutDis-, LTR+, OBFF Not Supported ARIFwd- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis- Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1- EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- Capabilities: [100 v1] Virtual Channel Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 Arb: Fixed- WRR32- WRR64- WRR128- Ctrl: ArbSelect=Fixed Status: InProgress- VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff Status: NegoPending- InProgress- Capabilities: [400 v1] L1 PM Substates L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1 + L1_PM_Substates+ PortCommonModeRestoreTime=30us PortTPowerOnTime=10us Capabilities: [600 v1] Latency Tolerance Reporting Max snoop latency: 0ns Max no snoop latency: 0ns Kernel driver in use: pcieport 01:00.0 Class 0200: Device 8086:1521 (rev 01) Subsystem: Device 1d1a:0000 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- TAbort- SERR- > Signed-off-by: Honghui Zhang > > --- > > drivers/pci/pcie/portdrv_pci.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/pci/pcie/portdrv_pci.c b/drivers/pci/pcie/portdrv_pci.c > > index eef22dc..86926ea 100644 > > --- a/drivers/pci/pcie/portdrv_pci.c > > +++ b/drivers/pci/pcie/portdrv_pci.c > > @@ -179,7 +179,7 @@ static void pcie_portdrv_err_resume(struct pci_dev *dev) > > */ > > static const struct pci_device_id port_pci_ids[] = { { > > /* handle any PCI-Express port */ > > - PCI_DEVICE_CLASS(((PCI_CLASS_BRIDGE_PCI << 8) | 0x00), ~0), > > + PCI_DEVICE_CLASS(((PCI_CLASS_BRIDGE_PCI << 8) | 0x00), ~0x01), > > }, { /* end: all zeroes */ } > > }; > > > > -- > > 2.6.4 > > > > > > _______________________________________________ > > linux-arm-kernel mailing list > > linux-arm-kernel@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel