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[209.132.180.67]) by mx.google.com with ESMTP id q83si10830538pfa.205.2019.02.11.23.43.39; Mon, 11 Feb 2019 23:43:54 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=cKoIwIfm; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727768AbfBLHnV (ORCPT + 99 others); Tue, 12 Feb 2019 02:43:21 -0500 Received: from lelv0143.ext.ti.com ([198.47.23.248]:39596 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726216AbfBLHnV (ORCPT ); Tue, 12 Feb 2019 02:43:21 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x1C7gxW4016192; Tue, 12 Feb 2019 01:42:59 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1549957379; bh=0BVQK2h7n5uAQP2tOjRTVbyO+5NEkhePJaOjylUmu8o=; h=From:To:CC:Subject:Date; b=cKoIwIfm9MOqPRVo6ui2ZoMw8ou8r4sa1mDtxULoqTHlR5k18psibxxjg78YPg5cr W1LBFDAMujP8NQpOGvutDR+ul7pLpN4ivgqQj83INIIyO3Sn6Hbn0H1ZqWkDlS18I6 AZbIH1YQFKOSgIEKWlZVzR5NMxALvRL0/SAI2IBE= Received: from DLEE106.ent.ti.com (dlee106.ent.ti.com [157.170.170.36]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x1C7gxKa019436 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 12 Feb 2019 01:42:59 -0600 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Tue, 12 Feb 2019 01:42:58 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Tue, 12 Feb 2019 01:42:58 -0600 Received: from uda0131933.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x1C7gsru000385; Tue, 12 Feb 2019 01:42:54 -0600 From: Lokesh Vutla To: , Tony Lindgren , Nishanth Menon , Santosh Shilimkar , Rob Herring , , CC: Linux ARM Mailing List , , Device Tree Mailing List , Sekhar Nori , Tero Kristo , Peter Ujfalusi , Lokesh Vutla Subject: [PATCH v5 00/10] Add support for TISCI irqchip drivers Date: Tue, 12 Feb 2019 13:12:27 +0530 Message-ID: <20190212074237.2875-1-lokeshvutla@ti.com> X-Mailer: git-send-email 2.19.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org TI AM65x SoC based on K3 architecture introduced support for Events which are message based interrupts with minimal latency. These events are not compatible with regular interrupts and are valid only through an event transport lane. An Interrupt Aggregator(INTA) is introduced to convert these events to interrupts. INTA can also group 64 events into a single interrupt. Now the SoC has many peripherals and a large number of event sources (time sync or DMA), the use of events is completely dependent on a user's specific application, which drives a need for maximum flexibility in which event sources are used in the system. It is also completely up to software control as to how the events are serviced. Because of the huge flexibility there are certain standard peripherals (like GPIO etc)where all interrupts cannot be directly corrected to host interrupt controller. For this purpose, Interrupt Router(INTR) is introduced in the SoC. INTR just does a classic interrupt redirection. So the SoC has 3 types of interrupt controllers: - GIC500 - Interrupt Router - Interrupt Aggregator Below is a diagrammatic view of how SoC integration of these interrupt controllers:(https://pastebin.ubuntu.com/p/9ngV3jdGj2/) Device Index-x Device Index-y | | | | .... \ / \ / \ (global events) / +---------------------------+ +---------+ | | | | | INTA | | GPIO | | | | | +---------------------------+ +---------+ | (vint) | | | \|/ | +---------------------------+ | | |<-------+ | INTR | | | +---------------------------+ | | \|/ (gic irq) +---------------------------+ | | | GIC | | | +---------------------------+ While at it, TISCI abstracts the handling of all above IRQ routes where interrupt sources are not directly connected to host interrupt controller. That would be configuration of Interrupt Aggregator and Interrupt Router. This series adds support for: - TISCI commands needed for IRQ configuration - Interrupt Router(INTR) and Interrupt Aggregator(INTA) drivers Changes since v4: - Mentioned the changes in each patch Changes since v3: - Fix documentation for Interrupt Router driver - Rebased on top of latest next. - Fully tested with DMA(using out of tree patches) - Fixed a build error with allmodconfig Grygorii Strashko (1): firmware: ti_sci: Add support to get TISCI handle using of_phandle Lokesh Vutla (8): firmware: ti_sci: Add support for RM core ops firmware: ti_sci: Add support for IRQ management dt-bindings: irqchip: Introduce TISCI Interrupt router bindings irqchip: ti-sci-intr: Add support for Interrupt Router driver dt-bindings: irqchip: Introduce TISCI Interrupt Aggregator bindings irqchip: ti-sci-inta: Add support for Interrupt Aggregator driver soc: ti: Add MSI domain support for K3 Interrupt Aggregator soc: ti: am6: Enable interrupt controller drivers Peter Ujfalusi (1): firmware: ti_sci: Add RM mapping table for am654 .../bindings/arm/keystone/ti,sci.txt | 3 +- .../interrupt-controller/ti,sci-inta.txt | 74 +++ .../interrupt-controller/ti,sci-intr.txt | 85 +++ MAINTAINERS | 6 + drivers/firmware/ti_sci.c | 536 ++++++++++++++++++ drivers/firmware/ti_sci.h | 102 ++++ drivers/irqchip/Kconfig | 23 + drivers/irqchip/Makefile | 2 + drivers/irqchip/irq-ti-sci-common.c | 131 +++++ drivers/irqchip/irq-ti-sci-common.h | 59 ++ drivers/irqchip/irq-ti-sci-inta.c | 531 +++++++++++++++++ drivers/irqchip/irq-ti-sci-intr.c | 315 ++++++++++ drivers/soc/ti/Kconfig | 11 + drivers/soc/ti/Makefile | 1 + drivers/soc/ti/k3_inta_msi.c | 143 +++++ include/linux/irqdomain.h | 1 + include/linux/msi.h | 7 + include/linux/soc/ti/k3_inta_msi.h | 21 + include/linux/soc/ti/ti_sci_protocol.h | 72 +++ 19 files changed, 2122 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.txt create mode 100644 drivers/irqchip/irq-ti-sci-common.c create mode 100644 drivers/irqchip/irq-ti-sci-common.h create mode 100644 drivers/irqchip/irq-ti-sci-inta.c create mode 100644 drivers/irqchip/irq-ti-sci-intr.c create mode 100644 drivers/soc/ti/k3_inta_msi.c create mode 100644 include/linux/soc/ti/k3_inta_msi.h -- 2.19.2