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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 22ffc791-f02c-4ca4-db71-08d69160980e X-MS-Exchange-CrossTenant-originalarrivaltime: 13 Feb 2019 03:08:49.6780 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR0402MB3724 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add i.MX8QXP CPU opp table to support cpufreq. Signed-off-by: Anson Huang --- arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/d= ts/freescale/imx8qxp.dtsi index 4c3dd95..3c27975 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -34,6 +34,14 @@ reg =3D <0x0 0x0>; enable-method =3D "psci"; next-level-cache =3D <&A35_L2>; + operating-points =3D < + /* kHz uV*/ + 1200000 1100000 + 900000 1000000 + >; + clocks =3D <&clk IMX_A35_CLK>; + clock-latency =3D <61036>; + #cooling-cells =3D <2>; }; =20 A35_1: cpu@1 { --=20 2.7.4