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[209.132.180.67]) by mx.google.com with ESMTP id i9si16280933plb.35.2019.02.13.01.26.45; Wed, 13 Feb 2019 01:27:01 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@broadcom.com header.s=google header.b=OxJmUX5z; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=broadcom.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732922AbfBMEwJ (ORCPT + 99 others); Tue, 12 Feb 2019 23:52:09 -0500 Received: from mail-wr1-f65.google.com ([209.85.221.65]:46968 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726095AbfBMEwJ (ORCPT ); Tue, 12 Feb 2019 23:52:09 -0500 Received: by mail-wr1-f65.google.com with SMTP id l9so875484wrt.13 for ; Tue, 12 Feb 2019 20:52:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=DXA/qvdpSx6JXTBhI/uFT9HoAq1/F1TFzcciALG1AYs=; b=OxJmUX5zQu5U6nrWnmxyDZyIuzCHbmDqxo+0G/z+Nh7rAVwTVumF8bRmnw87IP2bcW BQhkBgm0rrKU5HynC+ee43mZmGnYUX43ZJBtZqCGEJVMFhShcNudiFz8SDcEG74xNi3L LDUF92CzYPCWvmHvrkntBmg1uRdUNRpUNOly0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=DXA/qvdpSx6JXTBhI/uFT9HoAq1/F1TFzcciALG1AYs=; b=UTWM14qdsqmjE8YXU+bu1zgipfquE+tC6zo23mJ8kOv32PchKXsxxotx5Mhxn2Q6Q8 /d1ZbVAcAMxNRwac5YzWO6gGQ0EWDJIBDag58ED10C3TfitEywSDA5UJmSIB81nxY4Bx UT/F1EWcPVzEfa9IzzSIUT3Xn6S3MLEihGZA5swx6x3rbd8aQXYU1WT5Y89O3Aql7ZBq yWqbj8I8pe+JYoDWCXTmO9JpJ4vlButDlyoVs4/xH5RyO4yQvJL4Ak9LIdI0DWkQIytE Qp8lSuxmxymYwi3zdQCUOt78WYEArbRLq/xCq+7limib7kW8FdUQtt1JvQ9Df5xUyRom XOVg== X-Gm-Message-State: AHQUAub4ey8jxKK7Kwc/CKlbyIy73+z7ZsSq9x71DtIzOr/aireyAx8P 61fXySinulkooAoeTZqmSztGGflJpisAeHoTELMyWw== X-Received: by 2002:adf:f70c:: with SMTP id r12mr5684356wrp.54.1550033526805; Tue, 12 Feb 2019 20:52:06 -0800 (PST) MIME-Version: 1.0 References: <1549342622-9929-1-git-send-email-srinath.mannam@broadcom.com> <1549342622-9929-3-git-send-email-srinath.mannam@broadcom.com> <20190212183739.GB918@e107981-ln.cambridge.arm.com> In-Reply-To: <20190212183739.GB918@e107981-ln.cambridge.arm.com> From: Srinath Mannam Date: Wed, 13 Feb 2019 10:21:55 +0530 Message-ID: Subject: Re: [PATCH v2 2/2] PCI: iproc: Add PCIe 32bit outbound memory configuration To: Lorenzo Pieralisi Cc: Bjorn Helgaas , Ray Jui , Scott Branden , BCM Kernel Feedback , linux-pci@vger.kernel.org, iommu@lists.linux-foundation.org, Linux Kernel Mailing List , Abhishek Shah , Ray Jui Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Lorenzo, Thanks for review, please see my comments below inline. On Wed, Feb 13, 2019 at 12:07 AM Lorenzo Pieralisi wrote: > > On Tue, Feb 05, 2019 at 10:27:01AM +0530, Srinath Mannam wrote: > > Add configuration to support IPROC PCIe host controller outbound memory > > window mapping with SOC address range inside 4GB boundary, which is 32 bit > > AXI address. > > I do not understand what this means, explain it to me and rewrite the > commit log accordingly. > This is about "I/O regions" addressing given through ranges DT property. In the current driver "I/O regions" address mapping to corresponding PCI memory address in controller outbound registers is supports above 32-bit address. > What does this solve ? Why do we need this patch or rephrased, what > is missing in the current driver ? With this patch, If ranges DT property has below 32-bit I/O regions address then it will be added in the outbound mapping. This will help to access I/O region from CPU in 32-bit. I will update commit log and send next patch set. Ex: 1. ranges DT property for current driver is, ranges = <0x83000000 0x0 0x40000000 0x4 0x00000000 0 0x40000000>; I/O region address is 0x400000000 2. ranges DT property with this patch, ranges = <0x83000000 0x0 0x42000000 0x0 0x42000000 0 0x2000000>; I/O region address is 0x42000000 Regards, Srinath. > > > Signed-off-by: Srinath Mannam > > Signed-off-by: Abhishek Shah > > Signed-off-by: Ray Jui > > Reviewed-by: Scott Branden > > Reviewed-by: Vikram Prakash > > Review tags should be given on public mailing lists, these ones seem > to come from non-public review cycles in which case you must drop > them. > > > drivers/pci/controller/pcie-iproc.c | 21 +++++++++++++++++++-- > > 1 file changed, 19 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/pci/controller/pcie-iproc.c b/drivers/pci/controller/pcie-iproc.c > > index b882255..080f142 100644 > > --- a/drivers/pci/controller/pcie-iproc.c > > +++ b/drivers/pci/controller/pcie-iproc.c > > @@ -955,8 +955,25 @@ static int iproc_pcie_setup_ob(struct iproc_pcie *pcie, u64 axi_addr, > > resource_size_t window_size = > > ob_map->window_sizes[size_idx] * SZ_1M; > > > > - if (size < window_size) > > - continue; > > + /* > > + * Keep iterating until we reach the last window and > > + * with the minimal window size at index zero. In this > > + * case, we take a compromise by mapping it using the > > + * minimum window size that can be supported > > See above, I do not understand clearly what this means. > > Lorenzo > > > + */ > > + if (size < window_size) { > > + if (size_idx > 0 || window_idx > 0) > > + continue; > > + > > + /* > > + * For the corner case of reaching the minimal > > + * window size that can be supported on the > > + * last window > > + */ > > + axi_addr = ALIGN_DOWN(axi_addr, window_size); > > + pci_addr = ALIGN_DOWN(pci_addr, window_size); > > + size = window_size; > > + } > > > > if (!IS_ALIGNED(axi_addr, window_size) || > > !IS_ALIGNED(pci_addr, window_size)) { > > -- > > 2.7.4 > >