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[209.132.180.67]) by mx.google.com with ESMTP id c12si7357900pgh.257.2019.02.13.05.10.44; Wed, 13 Feb 2019 05:11:01 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JjA0P3vK; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389121AbfBMIih (ORCPT + 99 others); Wed, 13 Feb 2019 03:38:37 -0500 Received: from mail-lj1-f195.google.com ([209.85.208.195]:45254 "EHLO mail-lj1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1733035AbfBMIig (ORCPT ); Wed, 13 Feb 2019 03:38:36 -0500 Received: by mail-lj1-f195.google.com with SMTP id s5-v6so1230022ljd.12 for ; Wed, 13 Feb 2019 00:38:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=zeTngYgb/4MDOX0lTbENW3uviJ2EzDI0XEMt5X040V8=; b=JjA0P3vK4pOU7F5qrd3IeVvTQo9T4FfV7/zrrNxO0/NN1f+51FZB/ZNDvTn+at2cV7 j3WenQxHYUROFMA4bX2f9ScfUB83loKPLUN3va79aOuTSz49FJiedvCehrzu3ZhxvDwb 0Q8pkGq0hl6GFfBdcXq4RE5U06yA/6i2ows3PjVpwAWOKmplYH00hwuUiJ+rGGEv0C4F jDODiTT4nZ5NJUy7SC0dBSaX92aXY7NS22H8HS/Z4hA7mvadEB9N4MYWUJX7RnGK19dX E7oOPNH3Uwl4nU22HyNawHrPGCLN6Rym7BhZLz2qlLsz3/C3K6hrnBHFR7nzVvOlMA/f DHyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=zeTngYgb/4MDOX0lTbENW3uviJ2EzDI0XEMt5X040V8=; b=I0kd0diP+knFOyt5bJBvXo1Giz7USfBoBo3pafGIwfNKgNHAK7z6S+Lg3ek6QH3Cze CKk7sr3xGhuUfH/YqBqVOHaN17wxqiY7v+wjZp7vuua7QcQNPScqocO7Jo0Te1u0+/iD hY2cvraoVZyHQdQNGXtxiJ3wNAgGU6CJfre6l7oOkALjxwH78YbizrNi3cDdmAerXEtG qNBlJPDykVXorsAknRQush+PILsLj5G1iZjrK8nRLZ7xwfWb0zCM35YONLhfEgmC8Dfp xacMpi9jtjeXKW6y4RzcCpNovstV6VE+Xr+SOjKW+pGdmvBSaYTmz+EcOnC6cSZGY4qf OseQ== X-Gm-Message-State: AHQUAuaZepoQMj4AnnnBCwTinl4PeUUO54L8Lad6Y/YQR1SjH1OCCZF/ nTYYrmsDWar9vvoZtJr7udCiaFOH4LJI3ulefBWn7g== X-Received: by 2002:a2e:9087:: with SMTP id l7-v6mr4673657ljg.153.1550047114497; Wed, 13 Feb 2019 00:38:34 -0800 (PST) MIME-Version: 1.0 References: <20190208021631.30252-1-masneyb@onstation.org> In-Reply-To: <20190208021631.30252-1-masneyb@onstation.org> From: Linus Walleij Date: Wed, 13 Feb 2019 09:38:23 +0100 Message-ID: Subject: Re: [PATCH v2 00/11] qcom: ssbi-gpio: add support for hierarchical IRQ chip To: Brian Masney Cc: Stephen Boyd , Bjorn Andersson , Andy Gross , Marc Zyngier , Lee Jones , Thomas Gleixner , Shawn Guo , Doug Anderson , "open list:GPIO SUBSYSTEM" , Nicolas Dechesne , Niklas Cassel , David Brown , Rob Herring , Mark Rutland , "thierry.reding@gmail.com" , linux-arm-msm@vger.kernel.org, "linux-kernel@vger.kernel.org" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Feb 8, 2019 at 3:16 AM Brian Masney wrote: > This patch series adds hierarchical IRQ chip support to ssbi-gpio so > that device tree consumers can request an IRQ directly from the GPIO > block rather than having to request an IRQ from the underlying PMIC. > > For more background information, see the email thread with Linus > Walleij's excellent description of the problem at > https://www.spinics.net/lists/linux-gpio/msg34655.html. > > These changes were tested by Linus Walleij on an APQ8060 DragonBoard. > > See the notes on the individual patches for the changelog. SInce we have definitive ACKs from the irqchip and MFD maintainers I have queued this series on an immutable branch that I will merge for v5.1 and offer to the MFD and ARM SoC once it builds fine on the test servers. I don't think the Qcom maintainers will complain. Yours, Linus Walleij