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Signed-off-by: Anson Huang --- No change since V2. --- arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/d= ts/freescale/imx8qxp.dtsi index 4c3dd95..1e08387 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -34,6 +34,10 @@ reg =3D <0x0 0x0>; enable-method =3D "psci"; next-level-cache =3D <&A35_L2>; + clocks =3D <&clk IMX_A35_CLK>; + clock-latency =3D <61036>; + #cooling-cells =3D <2>; + operating-points-v2 =3D <&a35_0_opp_table>; }; =20 A35_1: cpu@1 { @@ -42,6 +46,7 @@ reg =3D <0x0 0x1>; enable-method =3D "psci"; next-level-cache =3D <&A35_L2>; + operating-points-v2 =3D <&a35_0_opp_table>; }; =20 A35_2: cpu@2 { @@ -50,6 +55,7 @@ reg =3D <0x0 0x2>; enable-method =3D "psci"; next-level-cache =3D <&A35_L2>; + operating-points-v2 =3D <&a35_0_opp_table>; }; =20 A35_3: cpu@3 { @@ -58,6 +64,7 @@ reg =3D <0x0 0x3>; enable-method =3D "psci"; next-level-cache =3D <&A35_L2>; + operating-points-v2 =3D <&a35_0_opp_table>; }; =20 A35_L2: l2-cache0 { @@ -65,6 +72,24 @@ }; }; =20 + a35_0_opp_table: opp-table { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-900000000 { + opp-hz =3D /bits/ 64 <900000000>; + opp-microvolt =3D <1000000>; + clock-latency-ns =3D <150000>; + }; + + opp-1200000000 { + opp-hz =3D /bits/ 64 <1200000000>; + opp-microvolt =3D <1100000>; + clock-latency-ns =3D <150000>; + opp-suspend; + }; + }; + gic: interrupt-controller@51a00000 { compatible =3D "arm,gic-v3"; reg =3D <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ --=20 2.7.4