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Wed, 13 Feb 2019 22:44:43 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=nXG4twRAkYaLsjmzwbjU3xDHne01mU65iLRlM2QjRzc=; b=Ccs+iViMP/2VevPmht7IOXV3Bikz5g6F1tuDKokTSIPPclsgz7Xeo5be2BcvVUuIA06JayjuKlc3MwxzH8k2alInZzW2Ur7V2e7ZzaBXmDrMQTiNlO9yS73LUYJiiUU18NSfrM7BmUmeXrndoNN8uaqOSlSQWwXTt6zOo6QKQUg= Received: from DB3PR0402MB3916.eurprd04.prod.outlook.com (52.134.72.18) by DB3PR0402MB3675.eurprd04.prod.outlook.com (52.134.69.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1601.17; Thu, 14 Feb 2019 03:44:37 +0000 Received: from DB3PR0402MB3916.eurprd04.prod.outlook.com ([fe80::14e8:6d2e:fe21:4fd5]) by DB3PR0402MB3916.eurprd04.prod.outlook.com ([fe80::14e8:6d2e:fe21:4fd5%3]) with mapi id 15.20.1601.023; Thu, 14 Feb 2019 03:44:37 +0000 From: Anson Huang To: "robh+dt@kernel.org" , "mark.rutland@arm.com" , "shawnguo@kernel.org" , "s.hauer@pengutronix.de" , "kernel@pengutronix.de" , "festevam@gmail.com" , "a.zummo@towertech.it" , "alexandre.belloni@bootlin.com" , Aisheng Dong , "ulf.hansson@linaro.org" , "sboyd@kernel.org" , Daniel Baluta , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-rtc@vger.kernel.org" CC: dl-linux-imx Subject: [PATCH V2 3/4] arm64: dts: freescale: imx8qxp: enable scu general irq channel Thread-Topic: [PATCH V2 3/4] arm64: dts: freescale: imx8qxp: enable scu general irq channel Thread-Index: AQHUxBebZGnL84gchEe72CRarVHnlw== Date: Thu, 14 Feb 2019 03:44:37 +0000 Message-ID: <1550115535-14488-4-git-send-email-Anson.Huang@nxp.com> References: <1550115535-14488-1-git-send-email-Anson.Huang@nxp.com> In-Reply-To: <1550115535-14488-1-git-send-email-Anson.Huang@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.7.4 x-clientproxiedby: HK0P153CA0020.APCP153.PROD.OUTLOOK.COM (2603:1096:203:18::32) To DB3PR0402MB3916.eurprd04.prod.outlook.com (2603:10a6:8:10::18) authentication-results: spf=none (sender IP is ) smtp.mailfrom=anson.huang@nxp.com; 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received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: GPtfJLXfLRjClICA1+vkmXbOAQ1OmK+ZsjoYm3BLsUvZKwFhaAWr0NRTw/98KUWwFprCBaMiZzi+FV/4ApBMG+KqYa7c5neTzcBNHkpk/QT68X8nuRD+e/veR8w1dhH52evFSIcT5WKqC4+2FiHRB3c3ijPlfySSY/x4j+38XF0XN0RAz/+KdUqWMYXkL+kCqLB7MdUmDQujA7WEGspn1d0FoICOPmYZqnxEt2lUgkXEilg8tVFboOKBV1pKaQdaM/thBW6VM6BZE/j7XFFUEGCbA5z0UIH1ZqUR7q9HEcyiQB8WCbU/cdFOQ4kAHncfQ4meQkcTwL1UuFd9oNzw/mR3PWeYK/piDVsZab4UUxJcMV09D11bpmCK5JTFgxQqvuL22viBlbM+nCicQLEjYDQR0FWY8Yyy1/IlZzWacrY= Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6b353fbf-88a3-4896-9da6-08d6922ebddf X-MS-Exchange-CrossTenant-originalarrivaltime: 14 Feb 2019 03:44:31.9576 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR0402MB3675 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On i.MX8QXP, SCU uses MU1 general interrupt channel #3 to notify user for IRQs of RTC alarm, thermal alarm and WDOG etc., mailbox RX doorbell mode is used for this function, this patch adds support for it. Signed-off-by: Anson Huang --- No change since V1. --- arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/d= ts/freescale/imx8qxp.dtsi index 1e08387..593e2db 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -112,7 +112,8 @@ scu { compatible =3D "fsl,imx-scu"; mbox-names =3D "tx0", "tx1", "tx2", "tx3", - "rx0", "rx1", "rx2", "rx3"; + "rx0", "rx1", "rx2", "rx3", + "gi3"; mboxes =3D <&lsio_mu1 0 0 &lsio_mu1 0 1 &lsio_mu1 0 2 @@ -120,7 +121,8 @@ &lsio_mu1 1 0 &lsio_mu1 1 1 &lsio_mu1 1 2 - &lsio_mu1 1 3>; + &lsio_mu1 1 3 + &lsio_mu1 3 3>; =20 clk: clock-controller { compatible =3D "fsl,imx8qxp-clk"; --=20 2.7.4