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[209.132.180.67]) by mx.google.com with ESMTP id 62si1983016pgb.298.2019.02.14.02.57.07; Thu, 14 Feb 2019 02:57:23 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2395473AbfBNEnA (ORCPT + 99 others); Wed, 13 Feb 2019 23:43:00 -0500 Received: from Mailgw01.mediatek.com ([1.203.163.78]:34523 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1730445AbfBNEm7 (ORCPT ); Wed, 13 Feb 2019 23:42:59 -0500 X-UUID: 6a4b683d0da54310ab7d957b35f80a18-20190214 X-UUID: 6a4b683d0da54310ab7d957b35f80a18-20190214 Received: from mtkcas34.mediatek.inc [(172.27.4.250)] by mailgw01.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 61265292; Thu, 14 Feb 2019 12:42:51 +0800 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by MTKMBS33N2.mediatek.inc (172.27.4.76) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 14 Feb 2019 12:42:49 +0800 Received: from mszsdclx1018.gcn.mediatek.inc (10.16.6.18) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 14 Feb 2019 12:42:48 +0800 From: Jitao Shi To: Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , , David Airlie , Matthias Brugger , CC: Jitao Shi , Thierry Reding , Ajay Kumar , Inki Dae , Rahul Sharma , Sean Paul , Vincent Palatin , Andy Yan , Philipp Zabel , Russell King , , , , , , , Sascha Hauer , , , , , , Subject: [PATCH 2/3] drm/mediatek: CMDQ reg address of mt8173 is different with mt2701 Date: Thu, 14 Feb 2019 12:42:42 +0800 Message-ID: <20190214044243.129920-2-jitao.shi@mediatek.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190214044243.129920-1-jitao.shi@mediatek.com> References: <20190214044243.129920-1-jitao.shi@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7BIT Content-Type: text/plain; charset=US-ASCII X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Config the different CMDQ reg address in driver data. Signed-off-by: Jitao Shi --- drivers/gpu/drm/mediatek/mtk_dsi.c | 39 ++++++++++++++++++++++++------ 1 file changed, 31 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index 93fa255b4aad..80db02a25cb0 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -156,6 +156,10 @@ struct phy; +struct mtk_dsi_driver_data { + const u32 reg_cmdq_off; +}; + struct mtk_dsi { struct mtk_ddp_comp ddp_comp; struct device *dev; @@ -182,6 +186,7 @@ struct mtk_dsi { bool enabled; u32 irq_data; wait_queue_head_t irq_wait_queue; + struct mtk_dsi_driver_data *driver_data; }; static inline struct mtk_dsi *encoder_to_dsi(struct drm_encoder *e) @@ -934,6 +939,7 @@ static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct mipi_dsi_msg *msg) const char *tx_buf = msg->tx_buf; u8 config, cmdq_size, cmdq_off, type = msg->type; u32 reg_val, cmdq_mask, i; + u32 reg_cmdq_off = dsi->driver_data->reg_cmdq_off; if (MTK_DSI_HOST_IS_READ(type)) config = BTA; @@ -953,9 +959,11 @@ static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct mipi_dsi_msg *msg) } for (i = 0; i < msg->tx_len; i++) - writeb(tx_buf[i], dsi->regs + DSI_CMDQ0 + cmdq_off + i); + mtk_dsi_mask(dsi, (reg_cmdq_off + cmdq_off + i) & (~0x3U), + (0xffUL << (((i + cmdq_off) & 3U) * 8U)), + tx_buf[i] << (((i + cmdq_off) & 3U) * 8U)); - mtk_dsi_mask(dsi, DSI_CMDQ0, cmdq_mask, reg_val); + mtk_dsi_mask(dsi, reg_cmdq_off, cmdq_mask, reg_val); mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, cmdq_size); } @@ -1074,10 +1082,27 @@ static const struct component_ops mtk_dsi_component_ops = { .unbind = mtk_dsi_unbind, }; +static const struct mtk_dsi_driver_data mt8173_dsi_driver_data = { + .reg_cmdq_off = 0x200, +}; + +static const struct mtk_dsi_driver_data mt2701_dsi_driver_data = { + .reg_cmdq_off = 0x180, +}; + +static const struct of_device_id mtk_dsi_of_match[] = { + { .compatible = "mediatek,mt2701-dsi", + .data = &mt2701_dsi_driver_data }, + { .compatible = "mediatek,mt8173-dsi", + .data = &mt8173_dsi_driver_data }, + { }, +}; + static int mtk_dsi_probe(struct platform_device *pdev) { struct mtk_dsi *dsi; struct device *dev = &pdev->dev; + const struct of_device_id *of_id; struct resource *regs; int irq_num; int comp_id; @@ -1101,6 +1126,10 @@ static int mtk_dsi_probe(struct platform_device *pdev) if (ret) goto err_unregister_host; + of_id = of_match_device(mtk_dsi_of_match, &pdev->dev); + dsi->driver_data = (struct mtk_dsi_driver_data *) + of_id->data; + dsi->engine_clk = devm_clk_get(dev, "engine"); if (IS_ERR(dsi->engine_clk)) { ret = PTR_ERR(dsi->engine_clk); @@ -1194,12 +1223,6 @@ static int mtk_dsi_remove(struct platform_device *pdev) return 0; } -static const struct of_device_id mtk_dsi_of_match[] = { - { .compatible = "mediatek,mt2701-dsi" }, - { .compatible = "mediatek,mt8173-dsi" }, - { }, -}; - struct platform_driver mtk_dsi_driver = { .probe = mtk_dsi_probe, .remove = mtk_dsi_remove, -- 2.20.1