Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
Subject: Re: [PATCH v5 05/10] dt-bindings: irqchip: Introduce TISCI Interrupt
 router bindings
To:     Tony Lindgren <tony@atomide.com>
CC:     <marc.zyngier@arm.com>, Nishanth Menon <nm@ti.com>,
        Santosh Shilimkar <ssantosh@kernel.org>,
        Rob Herring <robh+dt@kernel.org>, <tglx@linutronix.de>,
        <jason@lakedaemon.net>,
        Linux ARM Mailing List <linux-arm-kernel@lists.infradead.org>,
        <linux-kernel@vger.kernel.org>,
        Device Tree Mailing List <devicetree@vger.kernel.org>,
        Sekhar Nori <nsekhar@ti.com>, Tero Kristo <t-kristo@ti.com>,
        Peter Ujfalusi <peter.ujfalusi@ti.com>
References: <20190212074237.2875-1-lokeshvutla@ti.com>
 <20190212074237.2875-6-lokeshvutla@ti.com>
 <20190212163018.GL5720@atomide.com>
 <5b5d86b9-2aa7-718c-c1da-70bbf9bf589e@ti.com>
 <20190213153215.GT5720@atomide.com>
From:   Lokesh Vutla <lokeshvutla@ti.com>
Message-ID: <821ab540-469a-2166-9346-9cc0dec8ffbe@ti.com>
Date:   Thu, 14 Feb 2019 14:10:02 +0530
User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101
 Thunderbird/60.2.1
MIME-Version: 1.0
In-Reply-To: <20190213153215.GT5720@atomide.com>
Content-Type: text/plain; charset="utf-8"
Content-Language: en-US
Content-Transfer-Encoding: 7bit
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk


On 13/02/19 9:02 PM, Tony Lindgren wrote:
> * Lokesh Vutla <lokeshvutla@ti.com> [190213 04:23]:
>> Hi Tony,
>>
>> On 12/02/19 10:00 PM, Tony Lindgren wrote:
>>> Hi,
>>>
>>> * Lokesh Vutla <lokeshvutla@ti.com> [190212 07:43]:
>>>> +The Interrupt Router (INTR) module provides a mechanism to route M
>>>> +interrupt inputs to N interrupt outputs, where all M inputs are selectable
>>>> +to be driven per N output. There is one register per output (MUXCNTL_N) that
>>>> +controls the selection.
>>>> +
>>>> +
>>>> +                                 Interrupt Router
>>>> +                             +----------------------+
>>>> +                             |  Inputs     Outputs  |
>>>> +        +-------+            | +------+             |
>>>> +        | GPIO  |----------->| | irq0 |             |       Host IRQ
>>>> +        +-------+            | +------+             |      controller
>>>> +                             |    .        +-----+  |      +-------+
>>>> +        +-------+            |    .        |  0  |  |----->|  IRQ  |
>>>> +        | INTA  |----------->|    .        +-----+  |      +-------+
>>>> +        +-------+            |    .          .      |
>>>> +                             | +------+      .      |
>>>> +                             | | irqM |    +-----+  |
>>>> +                             | +------+    |  N  |  |
>>>> +                             |             +-----+  |
>>>> +                             +----------------------+
>>>
>>> Is this always one-to-one mapping or can the same interrupt be routed to
>>> multiple targets like to the SoC and some coprocessor?
>>
>> Yes, it is always one-to-one. Output of INTR can only be attached to one of the
>> processor.
> 
> OK
> 
>>>> +Configuration of these MUXCNTL_N registers is done by a system controller
>>>> +(like the Device Memory and Security Controller on K3 AM654 SoC). System
>>>> +controller will keep track of the used and unused registers within the Router.
>>>> +Driver should request the system controller to get the range of GIC IRQs
>>>> +assigned to the requesting hosts. It is the drivers responsibility to keep
>>>> +track of Host IRQs.
>>>> +
>>>> +Communication between the host processor running an OS and the system
>>>> +controller happens through a protocol called TI System Control Interface
>>>> +(TISCI protocol). For more details refer:
>>>> +Documentation/devicetree/bindings/arm/keystone/ti,sci.txt
>>>
>>> Care to describe a bit why the interrupts need to be routed by a system
>>> controller?
>>
>> K3 architecture defines a heterogeneous system where multiple heterogeneous
>> cores are serving its own usecases. Given that there are multiple ways in which
>> a device IRQ can be routed using INTR, like either it can be routed to HLOS
>> core(A53 int this case) or it can be routed to any other coprocessor available
>> in the system(like R5). If every sw running in each co-processor is allowed to
>> program this INTR then there is a high probability that one sw executing on one
>> core can damage other heterogeneous core.  Mainly to avoid this damage the
>> configuration of all the INTRs and INTAs are done in a centralized place(sysfw).
>> Any user for programming its IRQ route should send a message to sysfw with the
>> parameters. These parameters are policed by sysfw and does the configuration.
> 
> OK so maybe update the description along those lines saying it's
> a shared piece of hardware between various independent SoC
> clusters which may or may not be running Linux.

IMHO, SoC integration is out of scope of this document. If you insist I can add
the details.

Thanks and regards,
Lokesh