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Date:   Thu, 14 Feb 2019 10:43:06 +0000
Message-ID: <86r2caslad.wl-marc.zyngier@arm.com>
From:   Marc Zyngier <marc.zyngier@arm.com>
To:     Aaro Koskinen <aaro.koskinen@iki.fi>
Cc:     Thomas Gleixner <tglx@linutronix.de>,
        Jason Cooper <jason@lakedaemon.net>,
        <linux-kernel@vger.kernel.org>, <tomli@tomli.me>,
        "Rafael J. Wysocki" <rafael@kernel.org>,
        Ralf Baechle <ralf@linux-mips.org>,
        Paul Burton <paul.burton@mips.com>,
        James Hogan <jhogan@kernel.org>
Subject: Re: [PATCH] irqchip/i8259: fix shutdown order by moving syscore_ops registration
In-Reply-To: <20190207205812.GA11315@darkstar.musicnaut.iki.fi>
References: <20190206212608.27189-1-aaro.koskinen@iki.fi>
        <8492440b-b489-0ce1-865c-4505042cb061@arm.com>
        <20190207205812.GA11315@darkstar.musicnaut.iki.fi>
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On Thu, 07 Feb 2019 20:58:12 +0000,
Aaro Koskinen <aaro.koskinen@iki.fi> wrote:
> 
> Hi,
> 
> On Thu, Feb 07, 2019 at 08:56:37AM +0000, Marc Zyngier wrote:
> > On 06/02/2019 21:26, Aaro Koskinen wrote:
> > >  static void init_8259A(int auto_eoi)
> > >  {
> > >  	unsigned long flags;
> > > @@ -332,6 +324,7 @@ struct irq_domain * __init __init_i8259_irqs(struct device_node *node)
> > >  		panic("Failed to add i8259 IRQ domain");
> > >  
> > >  	setup_irq(I8259A_IRQ_BASE + PIC_CASCADE_IR, &irq2);
> > > +	register_syscore_ops(&i8259_syscore_ops);
> > >  	return domain;
> > >  }
> > >  
> > > 
> > 
> > Given that this is a change of behaviour that is likely to affect other
> > platforms (I see at least another 6 MIPS machines using the i8259),
> > could someone make sure that this doesn't cause any regression? This is
> > unlikely to affect the SGI boxes, as they predate any notion of power
> > management, but something like Malta could potentially be affected.
> 
> For shutdown, I don't think there are many syscore_ops users on these
> platforms. Actually I could find only two that I think could be used:
> 	- cpufreq (issue fixed by this patch, and Loongson is the only user
> 	  anyway)
> 	- leds-trigger
> 
> Then suspend/resume: i8259 doesn't implement suspend, so there is no
> change in behaviour. In resume it does PIC re-init, but syscore_resume()
> is done with interrupts disabled so the order shouldn't matter.

In the absence of any comment from the MIPS guys over the past week,
I've queued this. Please let me know should it break anything.

Thanks,

	M.

-- 
Jazz is not dead, it just smell funny.