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Subject: Re: [PATCH v2 01/14] dt-bindings: remoteproc: Add TI PRUSS bindings
To:     Roger Quadros <rogerq@ti.com>, Suman Anna <s-anna@ti.com>,
        "Davis, Andrew" <afd@ti.com>, Lokesh Vutla <lokeshvutla@ti.com>
Cc:     Linus Walleij <linus.walleij@linaro.org>,
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        David Lechner <david@lechnology.com>,
        "Nori, Sekhar" <nsekhar@ti.com>, Tero Kristo <t-kristo@ti.com>,
        nsaulnier@ti.com, jreeder@ti.com,
        Murali Karicheri <m-karicheri2@ti.com>,
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From:   Marc Zyngier <marc.zyngier@arm.com>
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Organization: ARM Ltd
Message-ID: <aaff678a-820c-279e-632e-1ad25953029d@arm.com>
Date:   Thu, 14 Feb 2019 15:51:24 +0000
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On 14/02/2019 15:44, Roger Quadros wrote:
> On 14/02/19 14:52, Marc Zyngier wrote:
>> On Thu, 14 Feb 2019 10:55:10 +0000,
>> Roger Quadros <rogerq@ti.com> wrote:
>>>
>>>
>>> On 14/02/19 10:37, Linus Walleij wrote:
>>>> On Thu, Feb 14, 2019 at 4:13 AM Suman Anna <s-anna@ti.com> wrote:
>>>>> [Me]
>>>>
>>>>>> To be able to use hierarchical interrupt domain in the kernel, the top
>>>>>> interrupt controller must use the hierarchical (v2) irqdomain, so
>>>>>> if this is anything else than the ARM GIC it will be an interesting
>>>>>> undertaking to handle this.
>>>>>
>>>>> These are interrupt lines coming towards the host processor running
>>>>> Linux and are directly connected to the ARM GIC. This INTC module is
>>>>> actually an PRUSS internal interrupt controller that can take in 64 (on
>>>>> most SoCs) external events/interrupt sources and multiplexing them
>>>>> through two layers of many-to-one events-to-intr channels &
>>>>> intr-channels-to-host interrupts. Couple of the host interrupts go to
>>>>> the PRU cores themselves while the remaining ones come out of the IP to
>>>>> connect to other GICs in the SoC.
>>>>
>>>> If the muxing is static (like set up once at probe) so that while
>>>> the system is running, there is one and one only event mapped to
>>>> the GIC from the component below it, then it is hierarchical.
>>>
>>> This is how it looks.
>>>
>>> [GIC]<---8---[INTC]<---64---[events from peripherals]
>>>
>>> The 8 interrupt lines from INTC to the GIC are 1:1 mapped and fixed
>>> per SoC.  The muxing between 64 inputs to INTC and its 8 outputs are
>>> programmable and might not necessarily be static per boot/probe as
>>> it depends on what firmware is loaded on the PRU.
>>
>> But the point is that at any given time, there are at most 8 out of 64
>> inputs that are used, right? You *never* end-up with two (or more) of
>> these "events" being multiplexed on a single output line.
>>
> 
> Since the INTC's internal logic allows assigning more than one event each outputs,
> at most all 64 events can be assigned to one output or distributed among the 8 outputs.

OK. Do you get individual masking and status bits for each input?

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...