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[209.132.180.67]) by mx.google.com with ESMTP id q70si3894850pgq.526.2019.02.14.17.33.19; Thu, 14 Feb 2019 17:33:37 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@wdc.com header.s=dkim.wdc.com header.b=GnCFv+Lw; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=wdc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2406676AbfBNSVI (ORCPT + 99 others); Thu, 14 Feb 2019 13:21:08 -0500 Received: from esa3.hgst.iphmx.com ([216.71.153.141]:8019 "EHLO esa3.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2404761AbfBNSVI (ORCPT ); Thu, 14 Feb 2019 13:21:08 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1550168467; x=1581704467; h=subject:to:cc:references:from:message-id:date: mime-version:in-reply-to:content-transfer-encoding; bh=Bo+VzpBFXXwdzwQHKYuR4+jxlAb8abN0EXR3PAVtxIQ=; b=GnCFv+LwKqFwzCjycah/vDXSkBWK/f6Q/VUhReZCmZ7wE0aMYoPvLKcf 5sIn/2N74FnP7tI5oaw4OKfCSw/ynpoRqSPzTEcfUgAwIyxAd301Nm8bG eIDNApZcwlqGWDHp+eUz0oMQoUCRaAvOMeXILBkfBpW5XOKxX5uDUqtY3 taIlWnM0OLxgyrI4Ht817YN5gZcr/3d6jqgDGKHRXZsysINnfob9Hgy3O 4i9WCB7NNi/waJCO2nGX9HzmrZsDlFhbHqdFaNsyAapLf2LHUwSNJ53r7 B3QGFFSwtkYCpgdjzntjS24GSIjrjVetFv6vxd8/slcgC9DhDh+1pXJwB Q==; X-IronPort-AV: E=Sophos;i="5.58,369,1544457600"; d="scan'208";a="106284464" Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 15 Feb 2019 02:21:06 +0800 Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP; 14 Feb 2019 09:59:39 -0800 Received: from c02v91rdhtd5.sdcorp.global.sandisk.com (HELO [10.111.66.47]) ([10.111.66.47]) by uls-op-cesaip02.wdc.com with ESMTP; 14 Feb 2019 10:21:07 -0800 Subject: Re: [v5 PATCH 6/8] clocksource/drivers/riscv: Add required checks during clock source init To: Daniel Lezcano , "linux-riscv@lists.infradead.org" Cc: Alan Kao , Albert Ou , Andreas Schwab , Anup Patel , Dmitriy Cherkasov , Guenter Roeck , Jason Cooper , Johan Hovold , "linux-kernel@vger.kernel.org" , Marc Zyngier , Palmer Dabbelt , Paul Walmsley , Thomas Gleixner References: <1550089092-28783-1-git-send-email-atish.patra@wdc.com> <1550089092-28783-7-git-send-email-atish.patra@wdc.com> From: Atish Patra Message-ID: Date: Thu, 14 Feb 2019 10:21:05 -0800 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.13; rv:60.0) Gecko/20100101 Thunderbird/60.5.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2/14/19 2:24 AM, Daniel Lezcano wrote: > On 13/02/2019 21:18, Atish Patra wrote: >> Currently, clocksource registration happens for an invalid cpu for >> non-smp kernels. This lead to kernel panic as cpu hotplug registration >> will fail for those cpus. Moreover, riscv_hartid_to_cpuid can return >> errors now. >> >> Do not proceed if hartid or cpuid is invalid. Take this opprtunity to >> print appropriate error strings for different failure cases. >> >> Signed-off-by: Atish Patra > > Hi Atish, > > I applied this patch for 5.1 with the typo fixed and the reviewed-by tags. > > -- Daniel > Thanks!! Regards, Atish >> --- >> drivers/clocksource/timer-riscv.c | 23 ++++++++++++++++++++--- >> 1 file changed, 20 insertions(+), 3 deletions(-) >> >> diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c >> index 43189220..e8163693 100644 >> --- a/drivers/clocksource/timer-riscv.c >> +++ b/drivers/clocksource/timer-riscv.c >> @@ -95,13 +95,30 @@ static int __init riscv_timer_init_dt(struct device_node *n) >> struct clocksource *cs; >> >> hartid = riscv_of_processor_hartid(n); >> + if (hartid < 0) { >> + pr_warn("Not valid hartid for node [%pOF] error = [%d]\n", >> + n, hartid); >> + return hartid; >> + } >> + >> cpuid = riscv_hartid_to_cpuid(hartid); >> + if (cpuid < 0) { >> + pr_warn("Invalid cpuid for hartid [%d]\n", hartid); >> + return cpuid; >> + } >> >> if (cpuid != smp_processor_id()) >> return 0; >> >> + pr_info("%s: Registering clocksource cpuid [%d] hartid [%d]\n", >> + __func__, cpuid, hartid); >> cs = per_cpu_ptr(&riscv_clocksource, cpuid); >> - clocksource_register_hz(cs, riscv_timebase); >> + error = clocksource_register_hz(cs, riscv_timebase); >> + if (error) { >> + pr_err("RISCV timer register failed [%d] for cpu = [%d]\n", >> + error, cpuid); >> + return error; >> + } >> >> sched_clock_register(riscv_sched_clock, >> BITS_PER_LONG, riscv_timebase); >> @@ -110,8 +127,8 @@ static int __init riscv_timer_init_dt(struct device_node *n) >> "clockevents/riscv/timer:starting", >> riscv_timer_starting_cpu, riscv_timer_dying_cpu); >> if (error) >> - pr_err("RISCV timer register failed [%d] for cpu = [%d]\n", >> - error, cpuid); >> + pr_err("cpu hp setup state failed for RISCV timer [%d]\n", >> + error); >> return error; >> } >> >> > >