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Wysocki" , Ralf Baechle , James Hogan Subject: Re: [PATCH] irqchip/i8259: fix shutdown order by moving syscore_ops registration Thread-Topic: [PATCH] irqchip/i8259: fix shutdown order by moving syscore_ops registration Thread-Index: AQHUvsMOMJyeIl+QdU28dl9y0o/lHaXU0iYAgApUdgCAAIYggA== Date: Thu, 14 Feb 2019 18:43:10 +0000 Message-ID: <20190214184309.f3zklkhv55c4z4g6@pburton-laptop> References: <20190206212608.27189-1-aaro.koskinen@iki.fi> <8492440b-b489-0ce1-865c-4505042cb061@arm.com> <20190207205812.GA11315@darkstar.musicnaut.iki.fi> <86r2caslad.wl-marc.zyngier@arm.com> In-Reply-To: <86r2caslad.wl-marc.zyngier@arm.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BYAPR05CA0036.namprd05.prod.outlook.com (2603:10b6:a03:c0::49) To MWHPR2201MB1277.namprd22.prod.outlook.com (2603:10b6:301:24::17) user-agent: NeoMutt/20180716 authentication-results: spf=none (sender IP is ) smtp.mailfrom=pburton@wavecomp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [67.207.99.198] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 9e81b5f6-5716-4361-c567-08d692ac44c0 x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600110)(711020)(4605077)(2017052603328)(7153060)(7193020);SRVR:MWHPR2201MB1183; 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received-spf: None (protection.outlook.com: wavecomp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: dFt3hPAisA98h5K3QklzPoi8iC072Mgyznb8EQMWbWSsCbxs/gLbpNIOow/IK/WE7dNSWfAc8+68xJk2PyuqYYEeo/583pCj8K1CVe6iXEjiqfHwUacMZ9turE4RMwWmRXyMOwWq+ut8d9pvoUZLiVJ/WSoHVfLd4ngap/ps/fAterLZQnIYQTIyBv8GS3xVhijzw4fQiC+6ExGn4Wm14VwmZGO2s/RE2h2NDVREduSquVWw1gHCue7i5vuV2V9I6FWnRyWLI6Q8ne3ZbJ32nW37IRmmzgV5AoYM3YK1U6SbuRRhOPogVp849f3Bf5b7i6EBvqefmcTHK6MqCxNvq2WujeD/G8JEhpgiKrWqnEdC3D3x98FQDCGkqAy3ipm8FT+xZOtQFXJHXG5pAJGR0Q47SRwjjV8QNkoRzGx+lSY= Content-Type: text/plain; charset="us-ascii" Content-ID: <6D5EEEE901C5C54F9F4FEE05B6848C62@namprd22.prod.outlook.com> Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: mips.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9e81b5f6-5716-4361-c567-08d692ac44c0 X-MS-Exchange-CrossTenant-originalarrivaltime: 14 Feb 2019 18:43:10.4427 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-id: 463607d3-1db3-40a0-8a29-970c56230104 X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR2201MB1183 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Marc, On Thu, Feb 14, 2019 at 10:43:06AM +0000, Marc Zyngier wrote: > On Thu, 07 Feb 2019 20:58:12 +0000, > Aaro Koskinen wrote: > > On Thu, Feb 07, 2019 at 08:56:37AM +0000, Marc Zyngier wrote: > > > On 06/02/2019 21:26, Aaro Koskinen wrote: > > > > static void init_8259A(int auto_eoi) > > > > { > > > > unsigned long flags; > > > > @@ -332,6 +324,7 @@ struct irq_domain * __init __init_i8259_irqs(st= ruct device_node *node) > > > > panic("Failed to add i8259 IRQ domain"); > > > > =20 > > > > setup_irq(I8259A_IRQ_BASE + PIC_CASCADE_IR, &irq2); > > > > + register_syscore_ops(&i8259_syscore_ops); > > > > return domain; > > > > } > > > > =20 > > > >=20 > > >=20 > > > Given that this is a change of behaviour that is likely to affect oth= er > > > platforms (I see at least another 6 MIPS machines using the i8259), > > > could someone make sure that this doesn't cause any regression? This = is > > > unlikely to affect the SGI boxes, as they predate any notion of power > > > management, but something like Malta could potentially be affected. > >=20 > > For shutdown, I don't think there are many syscore_ops users on these > > platforms. Actually I could find only two that I think could be used: > > - cpufreq (issue fixed by this patch, and Loongson is the only user > > anyway) > > - leds-trigger > >=20 > > Then suspend/resume: i8259 doesn't implement suspend, so there is no > > change in behaviour. In resume it does PIC re-init, but syscore_resume(= ) > > is done with interrupts disabled so the order shouldn't matter. >=20 > In the absence of any comment from the MIPS guys over the past week, > I've queued this. Please let me know should it break anything. Apologies for my sluggish response, but for what it's worth the patch looks reasonable at a glance. Malta is the only other I8259-using hardware that I technically have access to, but at this point Malta isn't actively used & it's really seen more as "the board QEMU defaults to" than a useful real hardware platform. Thanks, Paul