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[209.132.180.67]) by mx.google.com with ESMTP id i16si11582250pfi.192.2019.02.17.15.44.14; Sun, 17 Feb 2019 15:44:30 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b=nYmtdpu5; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727705AbfBQXnw (ORCPT + 99 others); Sun, 17 Feb 2019 18:43:52 -0500 Received: from mail-qk1-f193.google.com ([209.85.222.193]:36501 "EHLO mail-qk1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727024AbfBQXnv (ORCPT ); Sun, 17 Feb 2019 18:43:51 -0500 Received: by mail-qk1-f193.google.com with SMTP id o125so9048866qkf.3 for ; Sun, 17 Feb 2019 15:43:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=3ANnZaosomtu0eO0QJ89wPkXqbFXXuBOppyqsrgxGRY=; b=nYmtdpu5zEqhIF7OM4oCJACO/rz/y8uDDRgS2OUPlzkrNyYGykmEWswCOxmdHSG60g wecUbBbOKwm9NreKo/Y3ZUR19kpeAowIItD7PaokFsWEvXiBv2/WxSIH62quzREovOwp s5D26uxOGFLxEjMnKqvW0N8ucU2O50d9yJGIs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=3ANnZaosomtu0eO0QJ89wPkXqbFXXuBOppyqsrgxGRY=; b=W/uGpMWjxNjEFrqdrku+aA71ILKv828iY24W63UpMFn/PO0Ugzh8/jEJdo+yBHKD8y ZcZTe0ruBUT54V9p45D8H7kxKnCBlVRER7tOf0pwly5pUUPB/H1piytnd43Mu2OvEw4W N3wwTkp6P2NPmM8jOlP9BOFZlw/B5G3e6xs8Cqmw7Q7SA6iLYVccF2DFjVFTWWj9U6zk +3CzlCnfCFyGoDvX2sRG30OMANV7d1S5/DOyaHTG8amqAu7OGsFHjZ/G3H7620muKO+l gg/mAmI77hqDGhvdR4iA/9iDntUffXvg80Nsn2mDTHUh/4+xKwAN++asvnsll+gPhBhT c0gQ== X-Gm-Message-State: AHQUAuavrf/j507FHQgwPEMlWJHan1tRIdaJjXOCtGmAHBKrwfjJEACv GyjF2miHy/6Q57wa5r2OwyxBvq47j7/BdYWx+D+tJQ== X-Received: by 2002:a37:634b:: with SMTP id x72mr13039324qkb.151.1550447029715; Sun, 17 Feb 2019 15:43:49 -0800 (PST) MIME-Version: 1.0 References: <20190214044243.129920-1-jitao.shi@mediatek.com> <20190214044243.129920-3-jitao.shi@mediatek.com> <1550414892.5194.17.camel@mszsdaap41> In-Reply-To: <1550414892.5194.17.camel@mszsdaap41> From: Nicolas Boichat Date: Mon, 18 Feb 2019 07:43:38 +0800 Message-ID: Subject: Re: [PATCH 3/3] drm/mediatek: add mt8183 dsi driver support To: Jitao Shi Cc: Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , linux-pwm@vger.kernel.org, David Airlie , Matthias Brugger , Thierry Reding , Ajay Kumar , Inki Dae , Rahul Sharma , Sean Paul , Vincent Palatin , Andy Yan , Philipp Zabel , Russell King , devicetree@vger.kernel.org, lkml , dri-devel@lists.freedesktop.org, linux-arm Mailing List , "moderated list:ARM/Mediatek SoC support" , srv_heupstream@mediatek.com, Sascha Hauer , Yingjoe Chen , Eddie Huang , cawa cheng , =?UTF-8?B?QmliYnkgSHNpZWggKOisnea/n+mBoCk=?= , CK HU , stonea168@163.com Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, Feb 17, 2019 at 10:48 PM Jitao Shi wrote: > > On Thu, 2019-02-14 at 13:54 +0800, Nicolas Boichat wrote: > > On Thu, Feb 14, 2019 at 12:43 PM Jitao Shi wrote: > > > > > > MT8183 dsi has two changes with mt8173. > > > 1. Add the register double buffer control, but we no need it, So make > > > it default off. > > > > Can you describe a little bit more what this is about? That's shadow > > registers, right? > > > > Yes, it is shadow registers. > > Jitao > > > > 2. Add picture size control. > > > > > > Signed-off-by: Jitao Shi > > > --- > > > drivers/gpu/drm/mediatek/mtk_dsi.c | 20 +++++++++++++++++++- > > > 1 file changed, 19 insertions(+), 1 deletion(-) > > > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c > > > index 80db02a25cb0..20cb53f05d42 100644 > > > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c > > > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c > > > @@ -78,6 +78,7 @@ > > > #define DSI_VBP_NL 0x24 > > > #define DSI_VFP_NL 0x28 > > > #define DSI_VACT_NL 0x2C > > > +#define DSI_SIZE_CON 0x38 > > > #define DSI_HSA_WC 0x50 > > > #define DSI_HBP_WC 0x54 > > > #define DSI_HFP_WC 0x58 > > > @@ -131,7 +132,10 @@ > > > #define VM_CMD_EN BIT(0) > > > #define TS_VFP_EN BIT(5) > > > > > > -#define DSI_CMDQ0 0x180 > > > > As I said earlier, move this to 2/3. > > > > Thank for you review. > I'll move it to 2/3 next version. > > Best Regards > Jitao > > > > +#define DSI_SHADOW_DEBUG 0x190U > > > +#define FORCE_COMMIT BIT(0) > > > +#define BYPASS_SHADOW BIT(1) > > > + > > > #define CONFIG (0xff << 0) > > > #define SHORT_PACKET 0 > > > #define LONG_PACKET 2 > > > @@ -158,6 +162,7 @@ struct phy; > > > > > > struct mtk_dsi_driver_data { > > > const u32 reg_cmdq_off; > > > + bool has_size_ctl; > > > }; > > > > > > struct mtk_dsi { > > > @@ -426,6 +431,9 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi) > > > writel(vm->vfront_porch, dsi->regs + DSI_VFP_NL); > > > writel(vm->vactive, dsi->regs + DSI_VACT_NL); > > > > > > + if (dsi->driver_data->has_size_ctl) > > > + writel(vm->vactive << 16 | vm->hactive, dsi->regs + DSI_SIZE_CON); > > > + > > > horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10); > > > > > > if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) > > > @@ -595,6 +603,9 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) > > > } > > > > > > mtk_dsi_enable(dsi); > > > + > > > + /* DSI no need this double buffer, disable it when writing register */ > > > > "DSI does not need double buffering, disable it when writing register" > > > > I'll fix it next version. In that case, please say something about "shadow registers". (maybe it's just me, but usually double-buffering is associated with framebuffer data, not register settings) > > > + writel(FORCE_COMMIT | BYPASS_SHADOW, dsi->regs + DSI_SHADOW_DEBUG); > > > > So you do this on all MT* variants, is that ok? > > > > > mtk_dsi_reset_engine(dsi); > > > mtk_dsi_phy_timconfig(dsi); > > > > > > @@ -1090,11 +1101,18 @@ static const struct mtk_dsi_driver_data mt2701_dsi_driver_data = { > > > .reg_cmdq_off = 0x180, > > > }; > > > > > > +static const struct mtk_dsi_driver_data mt8183_dsi_driver_data = { > > > + .reg_cmdq_off = 0x200, > > > + .has_size_ctl = true, > > > +}; > > > + > > > static const struct of_device_id mtk_dsi_of_match[] = { > > > { .compatible = "mediatek,mt2701-dsi", > > > .data = &mt2701_dsi_driver_data }, > > > { .compatible = "mediatek,mt8173-dsi", > > > .data = &mt8173_dsi_driver_data }, > > > + { .compatible = "mediatek,mt8183-dsi", > > > + .data = &mt8183_dsi_driver_data }, > > > { }, > > > }; > > > > > > -- > > > 2.20.1 > > > > >