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From:   Arnd Bergmann <arnd@arndb.de>
Date:   Tue, 19 Feb 2019 14:01:50 +0100
Message-ID: <CAK8P3a0iM17ABoaFn9+KymZ-JkjM9hmBNDMyn6-A=s06p1fvnQ@mail.gmail.com>
Subject: Re: [RFC PATCH] docs/memory-barriers.txt: Rewrite "KERNEL I/O BARRIER
 EFFECTS" section
To:     Will Deacon <will.deacon@arm.com>
Cc:     Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
        linux-arch <linux-arch@vger.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        "Paul E. McKenney" <paulmck@linux.ibm.com>,
        Benjamin Herrenschmidt <benh@kernel.crashing.org>,
        Peter Zijlstra <peterz@infradead.org>,
        Andrea Parri <andrea.parri@amarulasolutions.com>,
        Daniel Lustig <dlustig@nvidia.com>,
        David Howells <dhowells@redhat.com>,
        Alan Stern <stern@rowland.harvard.edu>,
        Linus Torvalds <torvalds@linux-foundation.org>,
        Thomas Petazzoni <thomas.petazzoni@free-electrons.com>,
        Gregory CLEMENT <gregory.clement@free-electrons.com>,
        Russell King - ARM Linux <linux@armlinux.org.uk>
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On Tue, Feb 19, 2019 at 12:36 PM Will Deacon <will.deacon@arm.com> wrote:
> On Tue, Feb 19, 2019 at 12:31:50PM +0100, Arnd Bergmann wrote:
> > On Tue, Feb 19, 2019 at 11:27 AM Thomas Petazzoni
> > <thomas.petazzoni@bootlin.com> wrote:
> >
> > I think an example of this would be a driver using outb() to disable
> > an interrupt, and then relying on the the interrupt no longer happening
> > after the outb().
>
> Isn't that racy already? i.e. the interrupt could fire just before you
> disabled it, but not get delivered by the irq controller until after you'd
> disabled it at the device?

Probably, I had a hard enough time trying to come up with any example ;-)

One reference to non-posted transaction in a comment is in
drivers/net/ethernet/dec/tulip/de4x5.c:

/*
** The DE4X5 interrupt handler.
**
** I/O Read/Writes through intermediate PCI bridges are never 'posted',
** so that the asserted interrupt always has some real data to work with -
** if these I/O accesses are ever changed to memory accesses, ensure the
** STS write is read immediately to complete the transaction if the adapter
** is not on bus 0. Lost interrupts can still occur when the PCI bus load
** is high and descriptor status bits cannot be set before the associated
** interrupt is asserted and this routine entered.
*/

I found another comment in the via-rhine driver:

/* Beware of PCI posted writes */
#define IOSYNC  do { ioread8(ioaddr + StationAddr); } while (0)

this one is used in the chip reset function, and in the transmit
path.

       Arnd


     Arnd