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client-ip=137.71.25.55; helo=nwd2mta1.analog.com; Received: from nwd2mta1.analog.com (137.71.25.55) by CY1NAM02FT024.mail.protection.outlook.com (10.152.74.210) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.20.1643.11 via Frontend Transport; Tue, 19 Feb 2019 17:13:31 +0000 Received: from NWD2HUBCAS7.ad.analog.com (nwd2hubcas7.ad.analog.com [10.64.69.107]) by nwd2mta1.analog.com (8.13.8/8.13.8) with ESMTP id x1JHDV4u009334 (version=TLSv1/SSLv3 cipher=AES256-SHA bits=256 verify=OK); Tue, 19 Feb 2019 09:13:31 -0800 Received: from linux.ad.analog.com (10.50.1.179) by NWD2HUBCAS7.ad.analog.com (10.64.69.107) with Microsoft SMTP Server id 14.3.408.0; Tue, 19 Feb 2019 12:13:30 -0500 From: Stefan Popa To: , CC: Stefan Popa , , , , , , , Subject: [PATCH 2/6] iio: imu: adis16480: Add support for configurable drdy indicator Date: Tue, 19 Feb 2019 19:12:14 +0200 Message-ID: <1550596338-24220-3-git-send-email-stefan.popa@analog.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1550596338-24220-1-git-send-email-stefan.popa@analog.com> References: <1550596338-24220-1-git-send-email-stefan.popa@analog.com> MIME-Version: 1.0 Content-Type: text/plain X-ADIRoutedOnPrem: True X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:137.71.25.55;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(396003)(136003)(376002)(346002)(39860400002)(2980300002)(3190300001)(189003)(199004)(4326008)(305945005)(51416003)(50226002)(7696005)(106466001)(8676002)(76176011)(72206003)(50466002)(7636002)(106002)(246002)(316002)(54906003)(36756003)(478600001)(110136005)(16586007)(8936002)(48376002)(336012)(446003)(426003)(6346003)(2906002)(26005)(77096007)(11346002)(44832011)(186003)(356004)(116002)(126002)(5660300002)(476003)(486006)(2616005)(6666004)(47776003);DIR:OUT;SFP:1101;SCL:1;SRVR:DM5PR03MB3067;H:nwd2mta1.analog.com;FPR:;SPF:Pass;LANG:en;PTR:nwd2mail10.analog.com;MX:1;A:1; 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This patch adds the option to configure each DIOx pin as data ready indicator with positive or negative polarity by reading the 'interrupts' and 'interrupt-names' properties from the devicetree. The 'interrupt-names' property is optional, if it is not specified, then the factory default DIO2 data ready signal is used. Signed-off-by: Stefan Popa --- drivers/iio/imu/adis16480.c | 76 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/drivers/iio/imu/adis16480.c b/drivers/iio/imu/adis16480.c index d222188..38ba0c1 100644 --- a/drivers/iio/imu/adis16480.c +++ b/drivers/iio/imu/adis16480.c @@ -10,6 +10,7 @@ */ #include +#include #include #include #include @@ -109,6 +110,10 @@ #define ADIS16480_FIR_COEF_D(x) ADIS16480_FIR_COEF(0x0B, (x)) /* ADIS16480_REG_FNCTIO_CTRL */ +#define ADIS16480_DRDY_SEL_MSK GENMASK(1, 0) +#define ADIS16480_DRDY_SEL(x) FIELD_PREP(ADIS16480_DRDY_SEL_MSK, x) +#define ADIS16480_DRDY_POL_MSK BIT(2) +#define ADIS16480_DRDY_POL(x) FIELD_PREP(ADIS16480_DRDY_POL_MSK, x) #define ADIS16480_DRDY_EN_MSK BIT(3) #define ADIS16480_DRDY_EN(x) FIELD_PREP(ADIS16480_DRDY_EN_MSK, x) @@ -121,12 +126,26 @@ struct adis16480_chip_info { unsigned int accel_max_scale; }; +enum adis16480_int_pin { + ADIS16480_PIN_DIO1, + ADIS16480_PIN_DIO2, + ADIS16480_PIN_DIO3, + ADIS16480_PIN_DIO4 +}; + struct adis16480 { const struct adis16480_chip_info *chip_info; struct adis adis; }; +static const char * const adis16480_int_pin_names[4] = { + [ADIS16480_PIN_DIO1] = "DIO1", + [ADIS16480_PIN_DIO2] = "DIO2", + [ADIS16480_PIN_DIO3] = "DIO3", + [ADIS16480_PIN_DIO4] = "DIO4", +}; + #ifdef CONFIG_DEBUG_FS static ssize_t adis16480_show_firmware_revision(struct file *file, @@ -840,6 +859,59 @@ static const struct adis_data adis16480_data = { .enable_irq = adis16480_enable_irq, }; +static int adis16480_config_irq_pin(struct device_node *of_node, + struct adis16480 *st) +{ + struct irq_data *desc; + enum adis16480_int_pin pin; + unsigned int irq_type; + uint16_t val; + int i, irq = 0; + + desc = irq_get_irq_data(st->adis.spi->irq); + if (!desc) { + dev_err(&st->adis.spi->dev, "Could not find IRQ %d\n", irq); + return -EINVAL; + } + + /* Disable data ready */ + val = ADIS16480_DRDY_EN(0); + + /* + * Get the interrupt from the devicetre by reading the + * interrupt-names property. If it is not specified, use + * the default interrupt on DIO2 pin. + */ + pin = ADIS16480_PIN_DIO2; + for (i = 0; i < ARRAY_SIZE(adis16480_int_pin_names); i++) { + irq = of_irq_get_byname(of_node, adis16480_int_pin_names[i]); + if (irq > 0) { + pin = i; + break; + } + } + + val |= ADIS16480_DRDY_SEL(pin); + + /* + * Get the interrupt line behaviour. The data ready polarity can be + * configured as positive or negative, corresponding to + * IRQF_TRIGGER_RISING or IRQF_TRIGGER_FALLING respectively. + */ + irq_type = irqd_get_trigger_type(desc); + if (irq_type == IRQF_TRIGGER_RISING) { /* Default */ + val |= ADIS16480_DRDY_POL(1); + } else if (irq_type == IRQF_TRIGGER_FALLING) { + val |= ADIS16480_DRDY_POL(0); + } else { + dev_err(&st->adis.spi->dev, + "Invalid interrupt type 0x%x specified\n", irq_type); + return -EINVAL; + } + /* Write the data ready configuration to the FNCTIO_CTRL register */ + return adis_write_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, val); +} + static int adis16480_probe(struct spi_device *spi) { const struct spi_device_id *id = spi_get_device_id(spi); @@ -867,6 +939,10 @@ static int adis16480_probe(struct spi_device *spi) if (ret) return ret; + ret = adis16480_config_irq_pin(spi->dev.of_node, st); + if (ret) + return ret; + ret = adis_setup_buffer_and_trigger(&st->adis, indio_dev, NULL); if (ret) return ret; -- 2.7.4