Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
From:   Aisheng Dong <aisheng.dong@nxp.com>
To:     Anson Huang <anson.huang@nxp.com>,
        "robh+dt@kernel.org" <robh+dt@kernel.org>,
        "mark.rutland@arm.com" <mark.rutland@arm.com>,
        "shawnguo@kernel.org" <shawnguo@kernel.org>,
        "s.hauer@pengutronix.de" <s.hauer@pengutronix.de>,
        "kernel@pengutronix.de" <kernel@pengutronix.de>,
        "festevam@gmail.com" <festevam@gmail.com>,
        "a.zummo@towertech.it" <a.zummo@towertech.it>,
        "alexandre.belloni@bootlin.com" <alexandre.belloni@bootlin.com>,
        "ulf.hansson@linaro.org" <ulf.hansson@linaro.org>,
        Daniel Baluta <daniel.baluta@nxp.com>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>,
        "linux-rtc@vger.kernel.org" <linux-rtc@vger.kernel.org>
CC:     dl-linux-imx <linux-imx@nxp.com>
Subject: RE: [PATCH V3 1/4] dt-bindings: fsl: scu: add general interrupt
 support
Thread-Topic: [PATCH V3 1/4] dt-bindings: fsl: scu: add general interrupt
 support
Thread-Index: AQHUyACy8HmIYiPaSECjXHiTh1QyKKXoHWZg
Date:   Wed, 20 Feb 2019 05:33:26 +0000
Message-ID: <AM6PR04MB42159D22AC552CB81AEEF6DE807D0@AM6PR04MB4215.eurprd04.prod.outlook.com>
References: <1550545569-7197-1-git-send-email-Anson.Huang@nxp.com>
In-Reply-To: <1550545569-7197-1-git-send-email-Anson.Huang@nxp.com>
Accept-Language: zh-CN, en-US
Content-Language: en-US
received-spf: None (protection.outlook.com: nxp.com does not designate
 permitted sender hosts)
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: quoted-printable
MIME-Version: 1.0
X-MS-Exchange-CrossTenant-Network-Message-Id: f09f7e54-9e2b-49fe-10a3-08d696f4f050
X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Feb 2019 05:33:26.6488
 (UTC)
X-MS-Exchange-CrossTenant-fromentityheader: Hosted
X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635
X-MS-Exchange-CrossTenant-mailboxtype: HOSTED
X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR04MB5351
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

> From: Anson Huang
> Sent: Tuesday, February 19, 2019 11:11 AM
> Subject: [PATCH V3 1/4] dt-bindings: fsl: scu: add general interrupt supp=
ort
>=20
> Add scu general interrupt function support.
>=20
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
> ---
> No change since V2.
> ---
>  .../devicetree/bindings/arm/freescale/fsl,scu.txt      | 18
> ++++++++++++------
>  1 file changed, 12 insertions(+), 6 deletions(-)
>=20
> diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
> b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
> index f388ec6..e5def3e 100644
> --- a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
> +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
> @@ -22,9 +22,11 @@ Required properties:
>  -------------------
>  - compatible:	should be "fsl,imx-scu".
>  - mbox-names:	should include "tx0", "tx1", "tx2", "tx3",
> -			       "rx0", "rx1", "rx2", "rx3".
> -- mboxes:	List of phandle of 4 MU channels for tx and 4 MU channels
> -		for rx. All 8 MU channels must be in the same MU instance.
> +			       "rx0", "rx1", "rx2", "rx3",
> +			       "gi3".

Should it be optional as SCU firmware does not require it for normal functi=
on?

And as MU also support sending interrupt via GIRn register,
How about using gip3 to distinguish sending general purpose interrupt?

Regards
Dong Aisheng
> +- mboxes:	List of phandle of 4 MU channels for tx, 4 MU channels for
> +		rx, and 1 MU channel for general interrupt. All 9 MU channels
> +		must be in the same MU instance.
>  		Cross instances are not allowed. The MU instance can only
>  		be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users need
>  		to make sure use the one which is not conflict with other @@ -34,6
> +36,7 @@ Required properties:
>  		Channel 1 must be "tx1" or "rx1".
>  		Channel 2 must be "tx2" or "rx2".
>  		Channel 3 must be "tx3" or "rx3".
> +		General interrupt channel must be "gi3".

This can be:
		General interrupt Rx channel must be "gip3"

Regards
Dong Aisheng

>  		e.g.
>  		mboxes =3D <&lsio_mu1 0 0
>  			  &lsio_mu1 0 1
> @@ -42,7 +45,8 @@ Required properties:
>  			  &lsio_mu1 1 0
>  			  &lsio_mu1 1 1
>  			  &lsio_mu1 1 2
> -			  &lsio_mu1 1 3>;
> +			  &lsio_mu1 1 3
> +			  &lsio_mu1 3 3>;
>  		See Documentation/devicetree/bindings/mailbox/fsl,mu.txt
>  		for detailed mailbox binding.
>=20
> @@ -153,7 +157,8 @@ firmware {
>  	scu {
>  		compatible =3D "fsl,imx-scu";
>  		mbox-names =3D "tx0", "tx1", "tx2", "tx3",
> -			     "rx0", "rx1", "rx2", "rx3";
> +			     "rx0", "rx1", "rx2", "rx3",
> +			     "gi3";
>  		mboxes =3D <&lsio_mu1 0 0
>  			  &lsio_mu1 0 1
>  			  &lsio_mu1 0 2
> @@ -161,7 +166,8 @@ firmware {
>  			  &lsio_mu1 1 0
>  			  &lsio_mu1 1 1
>  			  &lsio_mu1 1 2
> -			  &lsio_mu1 1 3>;
> +			  &lsio_mu1 1 3
> +			  &lsio_mu1 3 3>;
>=20
>  		clk: clk {
>  			compatible =3D "fsl,imx8qxp-clk", "fsl,scu-clk";
> --
> 2.7.4