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received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: hKHoLd10rwzeOlyTta/ptUH38hFSi4fvwLJ5iRa3w/kLz42R6NaVQefCCAvjVT4pXsQYroEDqKJTqMaW4Kb2jUaURsrIsCusUUQTaLEwAI4kl62OJRp94SoFqXeC8GRSzAGqHSGq/enMjztXr6Tf1o7+Sxn52NrgpDMDHLzaVQ4sw6Wj5bjs4w8khccEBX9IIeZHcaroVGqnhoELv3T/12YX/baFFXP3FWlFmQwr3aMRWyktRX5ME9C4duqKievkzvswB8XppweKa/2ruQWUBdzorLlB2uvA9vf/ax0p5Yji+LZCoVdqOtvLejeLF/56OgAWCD2PXdgJnv0pQGsbN5Y724Uqy/gk11ztLWdZRvj3LyMS1VDYkDzGJqITW979lTSONUU3LuK+sU/SAbMp5QnXLLtrQu//Gyx828duWpk= Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: ac26a274-2f81-4f4a-5307-08d6974098d8 X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Feb 2019 14:34:57.9470 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR0402MB3900 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Removes below resources which were defined during pre-silicon phase and the real silicons do NOT have them, they have never been used, latest system controller firmware also removed them: IMX_SC_R_DC_0_CAPTURE0 IMX_SC_R_DC_0_CAPTURE1 IMX_SC_R_DC_0_INTEGRAL0 IMX_SC_R_DC_0_INTEGRAL1 IMX_SC_R_DC_0_FRAC1 IMX_SC_R_DC_1_CAPTURE0 IMX_SC_R_DC_1_CAPTURE1 IMX_SC_R_DC_1_INTEGRAL0 IMX_SC_R_DC_1_INTEGRAL1 IMX_SC_R_DC_1_FRAC1 IMX_SC_R_GPU_3_PID0 IMX_SC_R_M4_0_SIM IMX_SC_R_M4_0_WDOG IMX_SC_R_M4_1_SIM IMX_SC_R_M4_1_WDOG Signed-off-by: Anson Huang --- No changes since V2, just separate the patch to 2, 1 patch to remove resour= ces and the other is to add new resources. --- include/dt-bindings/firmware/imx/rsrc.h | 30 +++++++++++++++--------------= - 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/include/dt-bindings/firmware/imx/rsrc.h b/include/dt-bindings/= firmware/imx/rsrc.h index 4481f2d..32cce37 100644 --- a/include/dt-bindings/firmware/imx/rsrc.h +++ b/include/dt-bindings/firmware/imx/rsrc.h @@ -36,15 +36,15 @@ #define IMX_SC_R_DC_0_BLIT1 20 #define IMX_SC_R_DC_0_BLIT2 21 #define IMX_SC_R_DC_0_BLIT_OUT 22 -#define IMX_SC_R_DC_0_CAPTURE0 23 -#define IMX_SC_R_DC_0_CAPTURE1 24 +#define IMX_SC_R_UNUSED19 23 +#define IMX_SC_R_UNUSED5 24 #define IMX_SC_R_DC_0_WARP 25 -#define IMX_SC_R_DC_0_INTEGRAL0 26 -#define IMX_SC_R_DC_0_INTEGRAL1 27 +#define IMX_SC_R_UNUSED7 26 +#define IMX_SC_R_UNUSED8 27 #define IMX_SC_R_DC_0_VIDEO0 28 #define IMX_SC_R_DC_0_VIDEO1 29 #define IMX_SC_R_DC_0_FRAC0 30 -#define IMX_SC_R_DC_0_FRAC1 31 +#define IMX_SC_R_UNUSED20 31 #define IMX_SC_R_DC_0 32 #define IMX_SC_R_GPU_2_PID0 33 #define IMX_SC_R_DC_0_PLL_0 34 @@ -53,17 +53,17 @@ #define IMX_SC_R_DC_1_BLIT1 37 #define IMX_SC_R_DC_1_BLIT2 38 #define IMX_SC_R_DC_1_BLIT_OUT 39 -#define IMX_SC_R_DC_1_CAPTURE0 40 -#define IMX_SC_R_DC_1_CAPTURE1 41 +#define IMX_SC_R_UNUSED9 40 +#define IMX_SC_R_UNUSED10 41 #define IMX_SC_R_DC_1_WARP 42 -#define IMX_SC_R_DC_1_INTEGRAL0 43 -#define IMX_SC_R_DC_1_INTEGRAL1 44 +#define IMX_SC_R_UNUSED11 43 +#define IMX_SC_R_UNUSED12 44 #define IMX_SC_R_DC_1_VIDEO0 45 #define IMX_SC_R_DC_1_VIDEO1 46 #define IMX_SC_R_DC_1_FRAC0 47 -#define IMX_SC_R_DC_1_FRAC1 48 +#define IMX_SC_R_UNUSED13 48 #define IMX_SC_R_DC_1 49 -#define IMX_SC_R_GPU_3_PID0 50 +#define IMX_SC_R_UNUSED14 50 #define IMX_SC_R_DC_1_PLL_0 51 #define IMX_SC_R_DC_1_PLL_1 52 #define IMX_SC_R_SPI_0 53 @@ -303,8 +303,8 @@ #define IMX_SC_R_M4_0_UART 287 #define IMX_SC_R_M4_0_I2C 288 #define IMX_SC_R_M4_0_INTMUX 289 -#define IMX_SC_R_M4_0_SIM 290 -#define IMX_SC_R_M4_0_WDOG 291 +#define IMX_SC_R_UNUSED15 290 +#define IMX_SC_R_UNUSED16 291 #define IMX_SC_R_M4_0_MU_0B 292 #define IMX_SC_R_M4_0_MU_0A0 293 #define IMX_SC_R_M4_0_MU_0A1 294 @@ -323,8 +323,8 @@ #define IMX_SC_R_M4_1_UART 307 #define IMX_SC_R_M4_1_I2C 308 #define IMX_SC_R_M4_1_INTMUX 309 -#define IMX_SC_R_M4_1_SIM 310 -#define IMX_SC_R_M4_1_WDOG 311 +#define IMX_SC_R_UNUSED17 310 +#define IMX_SC_R_UNUSED18 311 #define IMX_SC_R_M4_1_MU_0B 312 #define IMX_SC_R_M4_1_MU_0A0 313 #define IMX_SC_R_M4_1_MU_0A1 314 --=20 2.7.4