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[209.132.180.67]) by mx.google.com with ESMTP id d19si1377154pgv.522.2019.02.20.09.30.59; Wed, 20 Feb 2019 09:31:15 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@c-s.fr header.s=mail header.b=cb9QxjQr; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726462AbfBTR3O (ORCPT + 99 others); Wed, 20 Feb 2019 12:29:14 -0500 Received: from pegase1.c-s.fr ([93.17.236.30]:1149 "EHLO pegase1.c-s.fr" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725806AbfBTR3M (ORCPT ); Wed, 20 Feb 2019 12:29:12 -0500 Received: from localhost (mailhub1-int [192.168.12.234]) by localhost (Postfix) with ESMTP id 444PjJ3zgxz9v0g4; Wed, 20 Feb 2019 18:29:08 +0100 (CET) Authentication-Results: localhost; dkim=pass reason="1024-bit key; insecure key" header.d=c-s.fr header.i=@c-s.fr header.b=cb9QxjQr; dkim-adsp=pass; dkim-atps=neutral X-Virus-Scanned: Debian amavisd-new at c-s.fr Received: from pegase1.c-s.fr ([192.168.12.234]) by localhost (pegase1.c-s.fr [192.168.12.234]) (amavisd-new, port 10024) with ESMTP id nohItnSTYpfc; Wed, 20 Feb 2019 18:29:08 +0100 (CET) Received: from messagerie.si.c-s.fr (messagerie.si.c-s.fr [192.168.25.192]) by pegase1.c-s.fr (Postfix) with ESMTP id 444PjJ2Qfpz9v0g0; Wed, 20 Feb 2019 18:29:08 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=c-s.fr; s=mail; t=1550683748; bh=oJYnubGJxtoq3azbdLhwwK1cIIERr+Sch6LNkaghcgo=; h=In-Reply-To:References:From:Subject:To:Cc:Date:From; b=cb9QxjQrNP/Eb6oMwHSKY/4pKe5xN6r0miIS8oKhquwf7e+n3CdeytUL/BUOwNnJR 8NuU1qp4DtbNqH/J+gAqKotRxHgDjLRVCZ9Bu25tq0nH0Gs10AqOaCF2DNIFRAtX1t OYVnpLuBI+YAk/aNVb7LNAvJDrMdfk/6BMtdKa60= Received: from localhost (localhost [127.0.0.1]) by messagerie.si.c-s.fr (Postfix) with ESMTP id 041CE8B84F; Wed, 20 Feb 2019 18:29:10 +0100 (CET) X-Virus-Scanned: amavisd-new at c-s.fr Received: from messagerie.si.c-s.fr ([127.0.0.1]) by localhost (messagerie.si.c-s.fr [127.0.0.1]) (amavisd-new, port 10023) with ESMTP id E4ArswxBqKy0; Wed, 20 Feb 2019 18:29:09 +0100 (CET) Received: from po16846vm.idsi0.si.c-s.fr (po15451.idsi0.si.c-s.fr [172.25.231.2]) by messagerie.si.c-s.fr (Postfix) with ESMTP id D861B8B84A; Wed, 20 Feb 2019 18:29:09 +0100 (CET) Received: by po16846vm.idsi0.si.c-s.fr (Postfix, from userid 0) id D9A686E85E; Wed, 20 Feb 2019 17:29:09 +0000 (UTC) Message-Id: In-Reply-To: References: From: Christophe Leroy Subject: [PATCH v3 03/16] powerpc/mm/32s: rework mmu_mapin_ram() To: Benjamin Herrenschmidt , Paul Mackerras , Michael Ellerman , j.neuschaefer@gmx.net Cc: linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org Date: Wed, 20 Feb 2019 17:29:09 +0000 (UTC) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch reworks mmu_mapin_ram() to be more generic and map as much blocks as possible. It now supports blocks not starting at address 0. It scans DBATs array to find free ones instead of forcing the use of BAT2 and BAT3. Signed-off-by: Christophe Leroy --- arch/powerpc/mm/ppc_mmu_32.c | 63 ++++++++++++++++++++++++++++---------------- 1 file changed, 41 insertions(+), 22 deletions(-) diff --git a/arch/powerpc/mm/ppc_mmu_32.c b/arch/powerpc/mm/ppc_mmu_32.c index b260ced065b4..5fc59b195fef 100644 --- a/arch/powerpc/mm/ppc_mmu_32.c +++ b/arch/powerpc/mm/ppc_mmu_32.c @@ -73,39 +73,58 @@ unsigned long p_block_mapped(phys_addr_t pa) return 0; } +static int find_free_bat(void) +{ + int b; + + if (cpu_has_feature(CPU_FTR_601)) { + for (b = 0; b < 4; b++) { + struct ppc_bat *bat = BATS[b]; + + if (!(bat[0].batl & 0x40)) + return b; + } + } else { + int n = mmu_has_feature(MMU_FTR_USE_HIGH_BATS) ? 8 : 4; + + for (b = 0; b < n; b++) { + struct ppc_bat *bat = BATS[b]; + + if (!(bat[1].batu & 3)) + return b; + } + } + return -1; +} + +static unsigned int block_size(unsigned long base, unsigned long top) +{ + unsigned int max_size = (cpu_has_feature(CPU_FTR_601) ? 8 : 256) << 20; + unsigned int base_shift = (fls(base) - 1) & 31; + unsigned int block_shift = (fls(top - base) - 1) & 31; + + return min3(max_size, 1U << base_shift, 1U << block_shift); +} + unsigned long __init mmu_mapin_ram(unsigned long base, unsigned long top) { - unsigned long tot, bl, done; - unsigned long max_size = (256<<20); + int idx; if (__map_without_bats) { printk(KERN_DEBUG "RAM mapped without BATs\n"); - return 0; + return base; } - /* Set up BAT2 and if necessary BAT3 to cover RAM. */ + while ((idx = find_free_bat()) != -1 && base != top) { + unsigned int size = block_size(base, top); - /* Make sure we don't map a block larger than the - smallest alignment of the physical address. */ - tot = top; - for (bl = 128<<10; bl < max_size; bl <<= 1) { - if (bl * 2 > tot) + if (size < 128 << 10) break; + setbat(idx, PAGE_OFFSET + base, base, size, PAGE_KERNEL_X); + base += size; } - setbat(2, PAGE_OFFSET, 0, bl, PAGE_KERNEL_X); - done = (unsigned long)bat_addrs[2].limit - PAGE_OFFSET + 1; - if ((done < tot) && !bat_addrs[3].limit) { - /* use BAT3 to cover a bit more */ - tot -= done; - for (bl = 128<<10; bl < max_size; bl <<= 1) - if (bl * 2 > tot) - break; - setbat(3, PAGE_OFFSET+done, done, bl, PAGE_KERNEL_X); - done = (unsigned long)bat_addrs[3].limit - PAGE_OFFSET + 1; - } - - return done; + return base; } /* -- 2.13.3