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[209.132.180.67]) by mx.google.com with ESMTP id 71si18422044pga.16.2019.02.21.02.11.48; Thu, 21 Feb 2019 02:12:04 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727632AbfBUKL0 (ORCPT + 99 others); Thu, 21 Feb 2019 05:11:26 -0500 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:4453 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725823AbfBUKLY (ORCPT ); Thu, 21 Feb 2019 05:11:24 -0500 Received: from pps.filterd (m0046037.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x1LA6sRO023425; Thu, 21 Feb 2019 11:11:12 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2qsbm9bt6j-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 21 Feb 2019 11:11:12 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 162A149; Thu, 21 Feb 2019 10:11:11 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas22.st.com [10.75.90.92]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 8E16B2858; Thu, 21 Feb 2019 10:11:10 +0000 (GMT) Received: from SAFEX1HUBCAS23.st.com (10.75.90.47) by Safex1hubcas22.st.com (10.75.90.92) with Microsoft SMTP Server (TLS) id 14.3.361.1; Thu, 21 Feb 2019 11:11:10 +0100 Received: from lmecxl0923.lme.st.com (10.48.0.237) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.361.1; Thu, 21 Feb 2019 11:11:09 +0100 From: Ludovic Barre To: Ulf Hansson , Rob Herring CC: , Maxime Coquelin , Alexandre Torgue , , , , , , Ludovic Barre Subject: [PATCH 2/2] mmc: mmci: add quirk property to add stm32 transfer mode Date: Thu, 21 Feb 2019 11:10:51 +0100 Message-ID: <1550743851-13588-3-git-send-email-ludovic.Barre@st.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1550743851-13588-1-git-send-email-ludovic.Barre@st.com> References: <1550743851-13588-1-git-send-email-ludovic.Barre@st.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.48.0.237] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2019-02-21_06:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ludovic Barre This patch adds a quirk bit to define specific stm32 transfer modes. sdmmc data transfer mode selection could be: -Block data transfer ending on block count. -SDIO multibyte data transfer. -MMC Stream data transfer (not used). -Block data transfer ending with STOP_TRANSMISSION command. Signed-off-by: Ludovic Barre --- drivers/mmc/host/mmci.c | 11 +++++++++++ drivers/mmc/host/mmci.h | 7 +++++++ 2 files changed, 18 insertions(+) diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index 387ff14..44c721a 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c @@ -284,6 +284,7 @@ static struct variant_data variant_stm32_sdmmc = { .datactrl_blocksz = 14, .stm32_idmabsize_mask = GENMASK(12, 5), .init = sdmmc_variant_init, + .quirks = MMCI_QUIRK_STM32_DTMODE, }; static struct variant_data variant_qcom = { @@ -1028,6 +1029,16 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) else datactrl = variant->datactrl_dpsm_enable | blksz_bits << 4; + if (variant->quirks & MMCI_QUIRK_STM32_DTMODE) { + if (host->mmc->card && mmc_card_sdio(host->mmc->card) && + data->blocks == 1) + datactrl |= MCI_DPSM_STM32_MODE_SDIO; + else if (data->stop && !host->mrq->sbc) + datactrl |= MCI_DPSM_STM32_MODE_BLOCK_STOP; + else + datactrl |= MCI_DPSM_STM32_MODE_BLOCK; + } + if (data->flags & MMC_DATA_READ) datactrl |= MCI_DPSM_DIRECTION; diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h index 474f4fa..9fbd0a4 100644 --- a/drivers/mmc/host/mmci.h +++ b/drivers/mmc/host/mmci.h @@ -131,6 +131,11 @@ /* Control register extensions in the Qualcomm versions */ #define MCI_DPSM_QCOM_DATA_PEND BIT(17) #define MCI_DPSM_QCOM_RX_DATA_PEND BIT(20) +/* Control register extensions in STM32 versions */ +#define MCI_DPSM_STM32_MODE_BLOCK (0 << 2) +#define MCI_DPSM_STM32_MODE_SDIO (1 << 2) +#define MCI_DPSM_STM32_MODE_STREAM (2 << 2) +#define MCI_DPSM_STM32_MODE_BLOCK_STOP (3 << 2) #define MMCIDATACNT 0x030 #define MMCISTATUS 0x034 @@ -357,6 +362,8 @@ struct variant_data { void (*init)(struct mmci_host *host); }; +#define MMCI_QUIRK_STM32_DTMODE BIT(0) + /* mmci variant callbacks */ struct mmci_host_ops { int (*validate_data)(struct mmci_host *host, struct mmc_data *data); -- 2.7.4