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Subject: Re: [EXT] [PATCH v6 2/2] mtd: spi-nor: cadence-quadspi: Add support
 for Octal SPI controller
To:     "Bean Huo (beanhuo)" <beanhuo@micron.com>,
        Boris Brezillon <bbrezillon@kernel.org>,
        "Tudor.Ambarus@microchip.com" <Tudor.Ambarus@microchip.com>
CC:     "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        "linux-mtd@lists.infradead.org" <linux-mtd@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Marek Vasut <marek.vasut@gmail.com>
References: <20190212083809.6534-1-vigneshr@ti.com>
 <20190212083809.6534-3-vigneshr@ti.com>
 <BYAPR08MB453362F4253ADA149D05315FDB7E0@BYAPR08MB4533.namprd08.prod.outlook.com>
From:   Vignesh R <vigneshr@ti.com>
Message-ID: <b459f797-d24c-5501-76a0-057ec1df594d@ti.com>
Date:   Thu, 21 Feb 2019 18:41:21 +0530
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On 21/02/19 4:11 PM, Bean Huo (beanhuo) wrote:
> Hi, Vignesh
> 
>>
>> Cadence OSPI controller IP supports Octal IO (x8 IO lines), It also has an
>> integrated PHY. IP register layout is very similar to existing QSPI IP except for
>> additional bits to support Octal and Octal DDR mode. Therefore, extend
>> current driver to support Octal mode. Only Octal SDR read (1-1-8)mode is
>> supported for now.
> 
> Does this your Cadence OSPI controller support 8-8-8 IO mode, if yes,
> Why not directly enable 8-8-8 mode? 
> 

Yes.. IP also supports 8-8-8 DTR mode. But supporting those modes
require enabling, configuring and calibrating OSPI PHY module within the
IP.
I am planning to do that, after moving driver over to spi-mem layer.


>> Tested with mt35xu512aba Octal flash on TI's AM654 EVM.
>>
>> Signed-off-by: Vignesh R <vigneshr@ti.com>
>> ______________________________________________________
>> Linux MTD discussion mailing list
>> http://lists.infradead.org/mailman/listinfo/linux-mtd/
> 
> ______________________________________________________
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> http://lists.infradead.org/mailman/listinfo/linux-mtd/
> 

-- 
Regards
Vignesh