Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: quoted-printable
Subject: Re: [PATCH v2] clk: fractional-divider: check parent rate only if flag is set
Message-ID: <155082319829.77512.7935951458664373330@swboyd.mtv.corp.google.com>
User-Agent: alot/0.8
References: <20190210153806.24201-1-katsuhiro@katsuster.net>
From:   Stephen Boyd <sboyd@kernel.org>
In-Reply-To: <20190210153806.24201-1-katsuhiro@katsuster.net>
To:     Katsuhiro Suzuki <katsuhiro@katsuster.net>,
        Michael Turquette <mturquette@baylibre.com>,
        linux-clk@vger.kernel.org
Cc:     Heiko Stuebner <heiko@sntech.de>,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
        Katsuhiro Suzuki <katsuhiro@katsuster.net>
Date:   Fri, 22 Feb 2019 00:13:18 -0800
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk

Quoting Katsuhiro Suzuki (2019-02-10 07:38:06)
> Custom approximation of fractional-divider may not need parent clock
> rate checking. For example Rockchip SoCs work fine using grand parent
> clock rate even if target rate is greater than parent.
>=20
> This patch checks parent clock rate only if CLK_SET_RATE_PARENT flag
> is set.
>=20
> For detailed example, clock tree of Rockchip I2S audio hardware.
>   - Clock rate of CPLL is 1.2GHz, GPLL is 491.52MHz.
>   - i2s1_div is integer divider can divide N (N is 1~128).
>     Input clock is CPLL or GPLL. Initial divider value is N =3D 1.
>     Ex) PLL =3D CPLL, N =3D 10, i2s1_div output rate is
>       CPLL / 10 =3D 1.2GHz / 10 =3D 120MHz
>   - i2s1_frac is fractional divider can divide input to x/y, x and
>     y are 16bit integer.
>=20
> CPLL --> | selector | ---> i2s1_div -+--> | selector | --> I2S1 MCLK

Applied to clk-next but I made the function into a macro because I don't
see the benefit to exporting such a simple thing.