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[209.132.180.67]) by mx.google.com with ESMTP id t62si818752pgd.369.2019.02.22.00.29.22; Fri, 22 Feb 2019 00:29:37 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727067AbfBVI2w (ORCPT + 99 others); Fri, 22 Feb 2019 03:28:52 -0500 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:13359 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1725944AbfBVI2u (ORCPT ); Fri, 22 Feb 2019 03:28:50 -0500 Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx08-00178001.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x1M8QehH018118; Fri, 22 Feb 2019 09:28:33 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2qpc6xsdjp-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Fri, 22 Feb 2019 09:28:33 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 10F5C31; Fri, 22 Feb 2019 08:28:33 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas21.st.com [10.75.90.44]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id DF6F628A8; Fri, 22 Feb 2019 08:28:32 +0000 (GMT) Received: from SAFEX1HUBCAS23.st.com (10.75.90.47) by SAFEX1HUBCAS21.st.com (10.75.90.44) with Microsoft SMTP Server (TLS) id 14.3.361.1; Fri, 22 Feb 2019 09:28:32 +0100 Received: from localhost (10.201.23.166) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.361.1; Fri, 22 Feb 2019 09:28:32 +0100 From: Christophe Roullier To: , , , , , , CC: , , , , , , Subject: [PATCH V2 6/8] dt-bindings: net: stmmac: add syscfg clock property Date: Fri, 22 Feb 2019 09:28:07 +0100 Message-ID: <1550824089-19961-7-git-send-email-christophe.roullier@st.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1550824089-19961-1-git-send-email-christophe.roullier@st.com> References: <1550824089-19961-1-git-send-email-christophe.roullier@st.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.201.23.166] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2019-02-22_06:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Need syscfg clock for MCU family in case bootloader does not activate it. Signed-off-by: Christophe Roullier --- Documentation/devicetree/bindings/net/stm32-dwmac.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.txt b/Documentation/devicetree/bindings/net/stm32-dwmac.txt index f42dc68..524f8a0 100644 --- a/Documentation/devicetree/bindings/net/stm32-dwmac.txt +++ b/Documentation/devicetree/bindings/net/stm32-dwmac.txt @@ -14,8 +14,8 @@ Required properties: - clock-names: Should be "stmmaceth" for the host clock. Should be "mac-clk-tx" for the MAC TX clock. Should be "mac-clk-rx" for the MAC RX clock. - For MPU family need to add also "ethstp" for power mode clock and, - "syscfg-clk" for SYSCFG clock. + Should be "syscfg-clk" for the SYSCFG clock. + For MPU family need to add also "ethstp" for power mode clock - interrupt-names: Should contain a list of interrupt names corresponding to the interrupts in the interrupts property, if available. Should be "macirq" for the main MAC IRQ -- 2.7.4