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[209.132.180.67]) by mx.google.com with ESMTP id b98si845441plb.230.2019.02.22.00.30.01; Fri, 22 Feb 2019 00:30:17 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727106AbfBVI3B (ORCPT + 99 others); Fri, 22 Feb 2019 03:29:01 -0500 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:45062 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726131AbfBVI2v (ORCPT ); Fri, 22 Feb 2019 03:28:51 -0500 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx08-00178001.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x1M8QYPV005498; Fri, 22 Feb 2019 09:28:36 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2qpc75hehk-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Fri, 22 Feb 2019 09:28:36 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 68BDA31; Fri, 22 Feb 2019 08:28:35 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas24.st.com [10.75.90.94]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 4224B28A8; Fri, 22 Feb 2019 08:28:35 +0000 (GMT) Received: from SAFEX1HUBCAS23.st.com (10.75.90.47) by Safex1hubcas24.st.com (10.75.90.94) with Microsoft SMTP Server (TLS) id 14.3.361.1; Fri, 22 Feb 2019 09:28:35 +0100 Received: from localhost (10.201.23.166) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.361.1; Fri, 22 Feb 2019 09:28:34 +0100 From: Christophe Roullier To: , , , , , , CC: , , , , , , Subject: [PATCH V2 8/8] ARM: dts: stm32: add syscfg clock support for Ethernet on STM32F429 SoC Date: Fri, 22 Feb 2019 09:28:09 +0100 Message-ID: <1550824089-19961-9-git-send-email-christophe.roullier@st.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1550824089-19961-1-git-send-email-christophe.roullier@st.com> References: <1550824089-19961-1-git-send-email-christophe.roullier@st.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.201.23.166] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2019-02-22_06:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch add syscfg clock support for Ethernet of the STM32F429 SoC. Needed if bootloader do not manage it. Signed-off-by: Christophe Roullier --- arch/arm/boot/dts/stm32f429.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index 8d6f028..6f78346 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -657,10 +657,12 @@ reg-names = "stmmaceth"; interrupts = <61>; interrupt-names = "macirq"; - clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx"; + clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx", + "syscfg-clk"; clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>, <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>, - <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>; + <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>, + <&rcc 0 STM32F4_APB2_CLOCK(SYSCFG)>; st,syscon = <&syscfg 0x4>; snps,pbl = <8>; snps,mixed-burst; -- 2.7.4