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Fri, 22 Feb 2019 04:43:12 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=4cH7PE7QtuTTLuMljKopNiYK+I7Lb/pD6UTzww/AMtw=; b=VuqyhVUaoovBcDO/kQ0xHN8RHSbiRFnVmqGDD8BEOGuiDzjtI2HLNBG6bLFpIHK9ozQ9DKJBEnebSrMDzbD0olHywghgLI3r8xCMqTGbi7e5PPgYdXUqUbRmNgkof9m44nxdNzXRQWeTFU+GL2NaYsEjNxd4/1fV8PKUXG4Ip6Y= Received: from DB3PR0402MB3916.eurprd04.prod.outlook.com (52.134.72.18) by DB3PR0402MB3756.eurprd04.prod.outlook.com (52.134.73.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1622.19; Fri, 22 Feb 2019 09:42:28 +0000 Received: from DB3PR0402MB3916.eurprd04.prod.outlook.com ([fe80::1cb4:3e1c:fc85:7ed7]) by DB3PR0402MB3916.eurprd04.prod.outlook.com ([fe80::1cb4:3e1c:fc85:7ed7%2]) with mapi id 15.20.1643.016; Fri, 22 Feb 2019 09:42:28 +0000 From: Anson Huang To: "robh+dt@kernel.org" , "mark.rutland@arm.com" , "shawnguo@kernel.org" , "s.hauer@pengutronix.de" , "kernel@pengutronix.de" , "festevam@gmail.com" , "mturquette@baylibre.com" , "sboyd@kernel.org" , "l.stach@pengutronix.de" , Abel Vesa , "ccaione@baylibre.com" , "agx@sigxcpu.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linux-clk@vger.kernel.org" CC: dl-linux-imx Subject: [PATCH 2/3] clk: imx8mq: add GPIO clocks to clock tree Thread-Topic: [PATCH 2/3] clk: imx8mq: add GPIO clocks to clock tree Thread-Index: AQHUypLsJex6bU8gwEKPZwhGnr6caA== Date: Fri, 22 Feb 2019 09:42:28 +0000 Message-ID: <1550828264-9962-2-git-send-email-Anson.Huang@nxp.com> References: <1550828264-9962-1-git-send-email-Anson.Huang@nxp.com> In-Reply-To: <1550828264-9962-1-git-send-email-Anson.Huang@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.7.4 x-clientproxiedby: HK2PR02CA0161.apcprd02.prod.outlook.com (2603:1096:201:1f::21) To DB3PR0402MB3916.eurprd04.prod.outlook.com (2603:10a6:8:10::18) authentication-results: spf=none (sender IP is ) smtp.mailfrom=anson.huang@nxp.com; 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received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: IxXjISnSiGn0e4ul6nALQeYUvGozhT65yStYxioZPQzroB5PyZRvZEUUMz79QS9nam0d9LinNtCx2OZdyPpLo2Q9WAL4OHfe5NjkjZ1Q1LTYgShqOStzJ43/Yh4UBaGtYQBC1CYuS46NNep6piqRyxx+EKTovpL4Qms0sWv4p78NWtG/0uQ7tggtpvrFtHYk1poQ2SdNPGirHQNadZJ4eDaC7jnmvCdDbDbWWvsQB1TgOapqxolS2wZgjjoVr0apPxIu/l2hZQDVDsrvr0RBMTfKRagUCyeC0A9JilKdMka6D3zbWirMP58kcceygHWnzXwkZE4C6q+hrVSQ23YcsqEI6UvKPlsIUkRCmRDBtFWDpLAfRfkOpozZzbrYsq1AtWWJhfXq+sYBeb5rWPffgQZDOCkHgXrnZbp1yWF9meU= Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: f96210c4-1307-4199-519a-08d698aa0ea9 X-MS-Exchange-CrossTenant-originalarrivaltime: 22 Feb 2019 09:42:22.5837 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR0402MB3756 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org i.MX8MQ has clock gate for each GPIO bank, add them into clock tree for GPIO driver to manage. Signed-off-by: Anson Huang --- drivers/clk/imx/clk-imx8mq.c | 5 +++++ include/dt-bindings/clock/imx8mq-clock.h | 8 +++++++- 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c index 2df1575..5839e45 100644 --- a/drivers/clk/imx/clk-imx8mq.c +++ b/drivers/clk/imx/clk-imx8mq.c @@ -498,6 +498,11 @@ static void __init imx8mq_clocks_init(struct device_no= de *np) clks[IMX8MQ_CLK_ECSPI2_ROOT] =3D imx_clk_gate4("ecspi2_root_clk", "ecspi2= ", base + 0x4080, 0); clks[IMX8MQ_CLK_ECSPI3_ROOT] =3D imx_clk_gate4("ecspi3_root_clk", "ecspi3= ", base + 0x4090, 0); clks[IMX8MQ_CLK_ENET1_ROOT] =3D imx_clk_gate4("enet1_root_clk", "enet_axi= ", base + 0x40a0, 0); + clks[IMX8MQ_CLK_GPIO1_ROOT] =3D imx_clk_gate4("gpio1_root_clk", "ipg_root= ", base + 0x40b0, 0); + clks[IMX8MQ_CLK_GPIO2_ROOT] =3D imx_clk_gate4("gpio2_root_clk", "ipg_root= ", base + 0x40c0, 0); + clks[IMX8MQ_CLK_GPIO3_ROOT] =3D imx_clk_gate4("gpio3_root_clk", "ipg_root= ", base + 0x40d0, 0); + clks[IMX8MQ_CLK_GPIO4_ROOT] =3D imx_clk_gate4("gpio4_root_clk", "ipg_root= ", base + 0x40e0, 0); + clks[IMX8MQ_CLK_GPIO5_ROOT] =3D imx_clk_gate4("gpio5_root_clk", "ipg_root= ", base + 0x40f0, 0); clks[IMX8MQ_CLK_GPT1_ROOT] =3D imx_clk_gate4("gpt1_root_clk", "gpt1", bas= e + 0x4100, 0); clks[IMX8MQ_CLK_I2C1_ROOT] =3D imx_clk_gate4("i2c1_root_clk", "i2c1", bas= e + 0x4170, 0); clks[IMX8MQ_CLK_I2C2_ROOT] =3D imx_clk_gate4("i2c2_root_clk", "i2c2", bas= e + 0x4180, 0); diff --git a/include/dt-bindings/clock/imx8mq-clock.h b/include/dt-bindings= /clock/imx8mq-clock.h index 04f7ac3..aff3335 100644 --- a/include/dt-bindings/clock/imx8mq-clock.h +++ b/include/dt-bindings/clock/imx8mq-clock.h @@ -391,5 +391,11 @@ =20 #define IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK 267 =20 -#define IMX8MQ_CLK_END 268 +#define IMX8MQ_CLK_GPIO1_ROOT 268 +#define IMX8MQ_CLK_GPIO2_ROOT 269 +#define IMX8MQ_CLK_GPIO3_ROOT 270 +#define IMX8MQ_CLK_GPIO4_ROOT 271 +#define IMX8MQ_CLK_GPIO5_ROOT 272 + +#define IMX8MQ_CLK_END 273 #endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */ --=20 2.7.4