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Fri, 22 Feb 2019 22:19:48 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=29jKVA1O7T+TQjOP1RYrhmq68HKrX4S93JGlP0REPyI=; b=tW68+OJGSIq2qwz7A39BVNzY/10gZm49sE56aNS/2wZh6RTcF/EGheQaxLYq52qy3WmFXYxDzv3gnKPQzVSd4NVty378GPaCWbY+F+Of/DnGpm19rwE3urSiH3h52LzyQgkasNFPg9Ye/u5XkGiAWdXykejGpHEbFBugOinklJc= Received: from DB3PR0402MB3916.eurprd04.prod.outlook.com (52.134.72.18) by DB3PR0402MB3659.eurprd04.prod.outlook.com (52.134.66.160) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1622.19; Sat, 23 Feb 2019 03:19:03 +0000 Received: from DB3PR0402MB3916.eurprd04.prod.outlook.com ([fe80::1cb4:3e1c:fc85:7ed7]) by DB3PR0402MB3916.eurprd04.prod.outlook.com ([fe80::1cb4:3e1c:fc85:7ed7%2]) with mapi id 15.20.1643.016; Sat, 23 Feb 2019 03:19:03 +0000 From: Anson Huang To: "robh+dt@kernel.org" , "mark.rutland@arm.com" , "shawnguo@kernel.org" , "s.hauer@pengutronix.de" , "kernel@pengutronix.de" , "festevam@gmail.com" , "mturquette@baylibre.com" , "sboyd@kernel.org" , "l.stach@pengutronix.de" , "ccaione@baylibre.com" , Abel Vesa , "agx@sigxcpu.org" , "baruch@tkos.co.il" , Jacky Bai , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linux-clk@vger.kernel.org" CC: dl-linux-imx Subject: [PATCH V2 1/2] clk: imx8mq: add GPIO clocks to clock tree Thread-Topic: [PATCH V2 1/2] clk: imx8mq: add GPIO clocks to clock tree Thread-Index: AQHUyyaGRBH6PMV7RkGGfcdev8mMpA== Date: Sat, 23 Feb 2019 03:19:03 +0000 Message-ID: <1550891665-29082-1-git-send-email-Anson.Huang@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.7.4 x-clientproxiedby: HK2PR04CA0082.apcprd04.prod.outlook.com (2603:1096:202:15::26) To DB3PR0402MB3916.eurprd04.prod.outlook.com (2603:10a6:8:10::18) authentication-results: spf=none (sender IP is ) smtp.mailfrom=anson.huang@nxp.com; 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received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: 5RgnqqvrpXUEEfDNsa8ItvgsIKi1IHhhUmPCL3k/rexlSF3jiIdUbcWz6h1Bv3vpVMyBMcBsLF+TE87tuuG7oZpC5wMSPddeIwA5/x2rMET7PlHNm0LOyqLmZxqeyOxuXW87c0WoytLTp0X9rfj3OUQOM0OTnlxEELKCzJav3z3L7OiwAgWodLl8AQNgfi8/dlNCw6ttppGLYQZuQ2JSVrZP4Z4Q43K6ND/uNVa0kI1HkWpgjAmXC0ApWB6TBeFXQi9LQV17z/4IPWTaUY3tVDKWwQB4zslKZoO9dUEVLJLA15L2SUtun0KTfZ6Gz5SwHrWygl9dOO9aPOeiGWMPQtxSlmKn6X8pUfl9udr6YInekQeFbiTYOT/irMNYxW4McnRvjSuoUSr/bqB586IohGEWt7Kfm2Wci1n+KpatkUs= Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: ebaf8d05-7fb5-4eb2-cd57-08d6993da91a X-MS-Exchange-CrossTenant-originalarrivaltime: 23 Feb 2019 03:18:57.1624 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR0402MB3659 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org i.MX8MQ has clock gate for each GPIO bank, add them into clock tree for GPIO driver to manage. Signed-off-by: Anson Huang --- No change since V1, just drop 1 patch from V1 patch series. --- drivers/clk/imx/clk-imx8mq.c | 5 +++++ include/dt-bindings/clock/imx8mq-clock.h | 8 +++++++- 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c index 26b57f4..553dcf5 100644 --- a/drivers/clk/imx/clk-imx8mq.c +++ b/drivers/clk/imx/clk-imx8mq.c @@ -500,6 +500,11 @@ static int imx8mq_clocks_probe(struct platform_device = *pdev) clks[IMX8MQ_CLK_ECSPI2_ROOT] =3D imx_clk_gate4("ecspi2_root_clk", "ecspi2= ", base + 0x4080, 0); clks[IMX8MQ_CLK_ECSPI3_ROOT] =3D imx_clk_gate4("ecspi3_root_clk", "ecspi3= ", base + 0x4090, 0); clks[IMX8MQ_CLK_ENET1_ROOT] =3D imx_clk_gate4("enet1_root_clk", "enet_axi= ", base + 0x40a0, 0); + clks[IMX8MQ_CLK_GPIO1_ROOT] =3D imx_clk_gate4("gpio1_root_clk", "ipg_root= ", base + 0x40b0, 0); + clks[IMX8MQ_CLK_GPIO2_ROOT] =3D imx_clk_gate4("gpio2_root_clk", "ipg_root= ", base + 0x40c0, 0); + clks[IMX8MQ_CLK_GPIO3_ROOT] =3D imx_clk_gate4("gpio3_root_clk", "ipg_root= ", base + 0x40d0, 0); + clks[IMX8MQ_CLK_GPIO4_ROOT] =3D imx_clk_gate4("gpio4_root_clk", "ipg_root= ", base + 0x40e0, 0); + clks[IMX8MQ_CLK_GPIO5_ROOT] =3D imx_clk_gate4("gpio5_root_clk", "ipg_root= ", base + 0x40f0, 0); clks[IMX8MQ_CLK_GPT1_ROOT] =3D imx_clk_gate4("gpt1_root_clk", "gpt1", bas= e + 0x4100, 0); clks[IMX8MQ_CLK_I2C1_ROOT] =3D imx_clk_gate4("i2c1_root_clk", "i2c1", bas= e + 0x4170, 0); clks[IMX8MQ_CLK_I2C2_ROOT] =3D imx_clk_gate4("i2c2_root_clk", "i2c2", bas= e + 0x4180, 0); diff --git a/include/dt-bindings/clock/imx8mq-clock.h b/include/dt-bindings= /clock/imx8mq-clock.h index 04f7ac3..aff3335 100644 --- a/include/dt-bindings/clock/imx8mq-clock.h +++ b/include/dt-bindings/clock/imx8mq-clock.h @@ -391,5 +391,11 @@ =20 #define IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK 267 =20 -#define IMX8MQ_CLK_END 268 +#define IMX8MQ_CLK_GPIO1_ROOT 268 +#define IMX8MQ_CLK_GPIO2_ROOT 269 +#define IMX8MQ_CLK_GPIO3_ROOT 270 +#define IMX8MQ_CLK_GPIO4_ROOT 271 +#define IMX8MQ_CLK_GPIO5_ROOT 272 + +#define IMX8MQ_CLK_END 273 #endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */ --=20 2.7.4