Received: by 2002:ac0:b08d:0:0:0:0:0 with SMTP id l13csp3971704imc; Sun, 24 Feb 2019 18:10:28 -0800 (PST) X-Google-Smtp-Source: AHgI3IZvjH49mAbIr59Q3XyX+a+C0P0t/3R+LEmKyVDJ+8TsUgf/URV6IwH6sl7DzzBX4WBN44hU X-Received: by 2002:aa7:92da:: with SMTP id k26mr17725441pfa.216.1551060628340; Sun, 24 Feb 2019 18:10:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1551060628; cv=none; d=google.com; s=arc-20160816; b=xFQk7otABSgtJQIQnCuVgn1ANkEzLfIQ/C2nmo9vNx4z9+bVjppEtTErORQm5p/b0n Hvlzhg9aTnIARE8HxUX0n+RiMGdtzRSIjatIMf2SFqOwnAZ83OkKe8VxqBINldklzj3v S4JuUjlU8m+gMFm03qW1TRH85bpaDGiogmFyIh3Eynsms6yb/lhVyIGI8e+IHsjlUCaJ delG2mBWvvgzt7rkgDbe5tBT23Y/Vuh9XhonkR/GCKOaGsMFTuAy6NyoqXKn2t0ZEgL4 Ec8KhOtL2+psI13aaYgQcETKWTgMZ9lPGwL9xfhxfCRZiCDgGzDiqvmfT5z7r323Emou 7Y4A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from; bh=5V1PKGXVvpUMFSyxBJKUaGR7H68PlplZ3PAVskodFf8=; b=xb04AMX7B4NI2iZfbWMARxbG0bKoOg2GWa+KmH2P2L+TqKBVyHfj1hdb62GDFvLwQp qjWcXXH7CHkc2IQdgs4EV6sDorh+hDJBXHc7F3L0Cr0w1yWITIXttS9shMOoSTmSDCCG /8DVU2e3L29O/SoEjO0B3tbOrjN2rSGWBMXaHzv8bK5yHitwDpAtNyEaoGjdrX+bsLDg oG5GDmYZ8Yse7kYkEhPFCUGCgsSRjw9lPgu6ArUDakiBxdV5rUQWuoCZoqOAWFTjMimW q5AQHtJ/aId+M3Z+W+FVDBNOcufrjusb9diOFclBhH5Iwg07deav2flcr4pKtMt9Fqjc 2TWA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f5si7954428pfn.259.2019.02.24.18.09.59; Sun, 24 Feb 2019 18:10:28 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728376AbfBYCJ0 (ORCPT + 99 others); Sun, 24 Feb 2019 21:09:26 -0500 Received: from mailgw02.mediatek.com ([1.203.163.81]:41282 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725991AbfBYCJZ (ORCPT ); Sun, 24 Feb 2019 21:09:25 -0500 X-UUID: 4108df188aa944f08e12e0f96e639957-20190225 X-UUID: 4108df188aa944f08e12e0f96e639957-20190225 Received: from mtkcas32.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 16261610; Mon, 25 Feb 2019 10:09:19 +0800 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by MTKMBS33N2.mediatek.inc (172.27.4.76) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 25 Feb 2019 10:09:18 +0800 Received: from mszsdaap41.mediatek.inc (172.27.4.253) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Mon, 25 Feb 2019 10:09:17 +0800 From: wangyan wang To: Michael Turquette , Stephen Boyd , CK Hu CC: wangyan wang , Matthias Brugger , Philipp Zabel , David Airlie , Daniel Vetter , chunhui dai , Colin Ian King , Sean Wang , Ryder Lee , , , , , , Subject: [PATCH V6 0/8] make mt7623 clock of hdmi stable Date: Mon, 25 Feb 2019 10:09:04 +0800 Message-ID: <20190225020912.29120-1-wangyan.wang@mediatek.com> X-Mailer: git-send-email 2.14.1 MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Wangyan Wang V6 adopt maintainer's suggestion. Here is the change list between V5 & V6 1. change "unsigned char mux_flags;" to "u8 mux_flags;" to match with the struct in " clk: mediatek: add MUX_GATE_FLAGS_2". chunhui dai (8): drm/mediatek: recalculate hdmi phy clock of MT2701 by querying hardware drm/mediatek: move the setting of fixed divider drm/mediatek: using different flags of clk for HDMI phy drm/mediatek: fix the rate and divder of hdmi phy for MT2701 clk: mediatek: add MUX_GATE_FLAGS_2 clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_sel drm/mediatek: using new factor for tvdpll in MT2701 drm/mediatek: fix the rate of parent for hdmi phy in MT2701 drivers/clk/mediatek/clk-mt2701.c | 4 +- drivers/clk/mediatek/clk-mtk.c | 2 +- drivers/clk/mediatek/clk-mtk.h | 20 ++++++--- drivers/gpu/drm/mediatek/mtk_dpi.c | 8 ++-- drivers/gpu/drm/mediatek/mtk_hdmi_phy.c | 34 ++++------------ drivers/gpu/drm/mediatek/mtk_hdmi_phy.h | 7 +--- drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c | 56 +++++++++++++++++++++++--- drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c | 23 +++++++++++ 8 files changed, 102 insertions(+), 52 deletions(-) -- 2.14.1