Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
MIME-Version: 1.0
References: <1550864500-13652-1-git-send-email-atish.patra@wdc.com> <1550864500-13652-7-git-send-email-atish.patra@wdc.com>
In-Reply-To: <1550864500-13652-7-git-send-email-atish.patra@wdc.com>
From:   Anup Patel <anup@brainfault.org>
Date:   Mon, 25 Feb 2019 09:05:17 +0530
Message-ID: <CAAhSdy3a_4sPUgDE8PjsvzpRx-i_mXrecLzjiagp9wZ7oUEVVw@mail.gmail.com>
Subject: Re: [v6 PATCH 6/6] RISC-V: Assign hwcap as per comman capabilities.
To:     Atish Patra <atish.patra@wdc.com>
Cc:     linux-riscv@lists.infradead.org, Alan Kao <alankao@andestech.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Andreas Schwab <schwab@suse.de>,
        Dmitriy Cherkasov <dmitriy@oss-tech.org>,
        Johan Hovold <johan@kernel.org>,
        "linux-kernel@vger.kernel.org List" <linux-kernel@vger.kernel.org>,
        Palmer Dabbelt <palmer@sifive.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Thomas Gleixner <tglx@linutronix.de>
Content-Type: text/plain; charset="UTF-8"
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk

On Sat, Feb 23, 2019 at 1:11 AM Atish Patra <atish.patra@wdc.com> wrote:
>
> Currently, we set hwcap based on first valid hart from DT. This may not
> be correct always as that hart might not be current booting cpu or may
> have a different capability.
>
> Set hwcap as the capabilities supported by all possible harts with "okay"
> status.
>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> ---
>  arch/riscv/kernel/cpufeature.c | 41 ++++++++++++++++++++++-------------------
>  1 file changed, 22 insertions(+), 19 deletions(-)
>
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index e7a4701f..bc29b010 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -20,6 +20,7 @@
>  #include <linux/of.h>
>  #include <asm/processor.h>
>  #include <asm/hwcap.h>
> +#include <asm/smp.h>
>
>  unsigned long elf_hwcap __read_mostly;
>  #ifdef CONFIG_FPU
> @@ -42,28 +43,30 @@ void riscv_fill_hwcap(void)
>
>         elf_hwcap = 0;
>
> -       /*
> -        * We don't support running Linux on hertergenous ISA systems.  For
> -        * now, we just check the ISA of the first "okay" processor.
> -        */
>         for_each_of_cpu_node(node) {
> -               if (riscv_of_processor_hartid(node) >= 0)
> -                       break;
> -       }
> -       if (!node) {
> -               pr_warn("Unable to find \"cpu\" devicetree entry\n");
> -               return;
> -       }
> +               unsigned long this_hwcap = 0;
>
> -       if (of_property_read_string(node, "riscv,isa", &isa)) {
> -               pr_warn("Unable to find \"riscv,isa\" devicetree entry\n");
> -               of_node_put(node);
> -               return;
> -       }
> -       of_node_put(node);
> +               if (riscv_of_processor_hartid(node) < 0)
> +                       continue;
>
> -       for (i = 0; i < strlen(isa); ++i)
> -               elf_hwcap |= isa2hwcap[(unsigned char)(isa[i])];
> +               if (of_property_read_string(node, "riscv,isa", &isa)) {
> +                       pr_warn("Unable to find \"riscv,isa\" devicetree entry\n");
> +                       continue;
> +               }
> +
> +               for (i = 0; i < strlen(isa); ++i)
> +                       this_hwcap |= isa2hwcap[(unsigned char)(isa[i])];
> +
> +               /*
> +                * All "okay" hart should have same isa. Set HWCAP based on
> +                * common capabilities of every "okay" hart, in case they don't
> +                * have.
> +                */
> +               if (elf_hwcap)
> +                       elf_hwcap &= this_hwcap;
> +               else
> +                       elf_hwcap = this_hwcap;
> +       }
>
>         /* We don't support systems with F but without D, so mask those out
>          * here. */
> --
> 2.7.4
>

Looks good to me.

Reviewed-by: Anup Patel <anup@brainfault.org>

Regards,
Anup